DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 03/04/2024 and 04/11/2023. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of Group II, Fig. 2A and 2B, as presented in claims 1-8 & 10-14 in the reply filed on 12/20/2025 is acknowledged.
Claim 9 & 15-22 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 12/20/2025.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by REDMAN-WHITE (WO 01/37422 A1, of record).
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Regarding claim 1, REDMAN-WHITE (Fig. 2) discloses a circuit with a pseudo class-AB structure, comprising:
an output stage (a stage includes transistors T1 and T2), having a first PMOS (transistors T1, PMOS) and a first NMOS (transistor T2, NMOS), wherein a first connection node between a drain terminal of the first PMOS (PMOS transistor T1) and a drain terminal of the first NMOS (NMOS transistor T2) is coupled to a first output terminal (output terminal 2) of the circuit;
a first capacitor (capacitor C3), coupled between a gate terminal of the first PMOS (transistor T1) and a gate terminal of the first NMOS (transistor T2); and
a first impedance component (resistor R1), coupled in parallel with the first capacitor (C3) between the gate terminal of the first PMOS (T1) and the gate terminal of the first NMOS (T2).
Allowable Subject Matter
Claims 2-8 & 10-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 6392485 B1, Doi (Fig. 1) discloses an amplifier comprising an output stage includes transistors M15 and M16 wherein a resistor R2 being connected between gate terminals of the transistors M15 and M16.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843