Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 9 (and dependent claims 10-12 and 17-18 dependent therefrom), 13 (and dependent claims 14-16 dependent therefrom), and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4 recites the limitation “the BGA” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 4 is interpreted in the instant Office action as follows: “the BGA” is equivalent to “the BGA package” based on antecedence in claim 1. This interpretation is to be confirmed by applicant in the next office action.
Claim 9 recites the limitation “the BGA” in lines 13 and 16. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 9 is interpreted in the instant Office action as follows: “the BGA” is equivalent to “the BGA package” based on antecedence in line 6. This interpretation is to be confirmed by applicant in the next office action.
Claim 13 recites the limitation “the BGA” in line 12 and “the IC, BGA” in line 15. There is insufficient antecedent basis for “BGA” as recited in the claim. For the sake of compact prosecution, claim 13 is interpreted in the instant Office action as follows: “the BGA” and “BGA” are equivalent to “the BGA package” and “BGA package” based on antecedence in line 5. This interpretation is to be confirmed by applicant in the next office action.
Claim 16 recites the limitation “the BGA” in line 2. There is insufficient antecedent basis for this limitation in the claim. For the sake of compact prosecution, claim 16 is interpreted in the instant Office action as follows: “the BGA” is equivalent to “the BGA package” based on antecedence in claim 13. This interpretation is to be confirmed by applicant in the next office action.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-8 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Liao (US 20230352381 A1).
Regarding claim 1, Liao discloses a circuit assembly (Fig. 18), comprising:
an integrated circuit (IC) (900) with a plurality of connection pads (928);
a ball grid array (BGA) package (200. Note: 200 contains several distinct structures combined as a single unit, i.e. structures 242, 210, 262; thus, it is a package) including a plurality of solder balls (290) arranged in an array (the array shown in top-down view in any of Figs. 17B-17E), wherein the plurality of solder balls are configured to connect the plurality of connections pads of the IC to a plurality of connections pads (180. Note: balls 290 connect pads 928 indirectly to pads 180 through intervening 200) on a printed circuit board (PCB) (100); and
a BGA spacer (one of 270) configured to fit among the plurality of solder balls (270 and 290 fit among each other, thus the spacer is “configured” as claimed),
wherein the BGA spacer has a width based upon a height and spacing of the plurality of solder balls (width is related to height by a ratio; [0110]: “length-to-width ratio”. Thus, width and height are “based upon” each other. Additionally, “width” and “height” are each related to the same solder balls and therefore the sizes of all three of these features are related to each other. Width is related to solder ball spacing because the spacer is located between them, as shown in Figs. 17B-17E. Height is related to solder ball height by [0110]: “not greater than, and may be the same as, or may be less than, the separation distance between”)
and a height based upon a height and spacing of the plurality of solder balls (height is related to width by a ratio; [0110]: “length-to-width ratio”. Thus, width and height are “based upon” each other. Additionally, “width” and “height” are each related to the same solder balls and therefore the sizes of all three of these features are related to each other. Height is related to solder ball height by [0110]: “not greater than, and may be the same as, or may be less than, the separation distance between”. Height is related to solder ball spacing by being located between the solder balls)
and a minimum distance between the IC and the PCB (See annotated figure. This distance is vertically between the IC and the PCB) to prevent shorting of adjacent solder balls (the solder balls are illustrated as having shorting prevented, i.e., none are directly shorted; [0044]: “may eliminate or reduce bumps-joint bridges”).
Illustrated below is a marked and annotated figure of Fig. 18 of Liao.
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Regarding claim 2, Liao discloses the circuit assembly of claim 1 (Fig. 18), further comprising a plurality of additional BGA spacers (additional 270 are included, at least one of which is shown in Fig. 18. Cross-sectional view Fig. 17B shows enough spacers to include a plurality in addition to the originally cited spacer because 4 are shown.) configured to fit among the plurality of solder balls, wherein the additional BGA spacers have a height and width based upon a height and spacing of the plurality of solder balls (as reasoned and cited in the claim 1 rejection).
Regarding claim 3, Liao discloses the circuit assembly of claim 2 (Fig. 17B), wherein the BGA spacer and one of the plurality of BGA spacers have a different shape (selecting two differently oriented groupings of 270 as “the BGA spacer” and “the plurality of BGA spacers”. These differently oriented groupings have different dimensions from each other in the hd1 and hd2 directions, thus “a different shape”).
Regarding claim 4 as noted in the 112(b) rejection, Liao discloses the circuit assembly of claim 1, wherein the BGA spacer is located among the plurality of solder balls at a location where the distance between the IC and the BGA package (“the distance” is referring to situations where the spacer hasn’t been included. The prior art is cited below as preventing warping, thus preventing this actual distance. This interpretation is consistent with Applicant’s use of these claim terms in [0007]) is less than a minimum distance between the IC and the PCB (See annotated figure, using the same minimum distance measurement markings cited in claim 1. This distance is vertically between the IC and the PCB.) to prevent shorting of adjacent solder balls due to warpage of the IC (the solder balls are illustrated as having shorting prevented, i.e., none are directly shorted; [0044]: “to prevent and/or reduce warpage of the chip package”).
Regarding claim 5, Liao discloses the circuit assembly of claim 1 (Fig. 18), wherein the BGA spacer is an interstitial type BGA spacer (relying on the plain and ordinary meaning of interstitial, where 270 is situated within a portion of the separation between the IC and the PCB).
Regarding claim 6, Liao discloses the circuit assembly of claim 1 (Fig. 17B), wherein the BGA spacer is one of a bar spacer, Lspacer, T-spacer, cross spacer, and X-spacer (lower-case L is illustrated).
Regarding claim 7, Liao discloses the circuit assembly of claim 1 (Fig. 17B), wherein the BGA spacer is an enclosure type BGA spacer (partial enclosure in the hd1/hd2 plane).
Regarding claim 8, Liao discloses the circuit assembly of claim 1 (Fig. 18), wherein the BGA spacer is one of a square spacer, rectangle spacer, triangle spacer, diamond spacer, and polygon spacer (a rectangular shape is illustrated in cross-sectional view of Fig. 18).
Claims 9, 11-13, and 15-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gowda (US 20230299012 A1).
Regarding independent claim 9 as noted in the 112(b) rejection, Gowda discloses a method of assembling a circuit assembly (Fig. 1A), comprising:
characterizing warpage characteristics ([0037]: “may depend on a degree of counter warpage/balance needed to cancel or minimize warpage”) of an integrated circuit (IC) (114-1) with a plurality of connection pads (124);
determining a location of a ball grid array (BGA) spacer (180; [0037]: “determined”) among a plurality of solder balls (130, a plurality is arranged in an array as shown in Fig. 1B) that are part of a BGA package (102. Note: 102 contains several distinct structures combined as a single unit, i.e. the wirings and layers described in [0042]; thus, it is a package) attached to the IC, based upon the warpage characteristics of the IC ([0037]: “to cancel or minimize warpage”);
determining a shape and dimensions of the BGA spacer based upon a height and spacing of the plurality of solder balls ([0037]: “a height (e.g., z-direction or a thickness) of the stiffener 180 may be between 20% and 80% of a second level interconnect 130 height”. Note: the BGA spacer 180 is located within the solder ball spacing),
wherein a height of the BGA spacer is further based upon a minimum distance (See annotated figure 1A. This distance is vertically between the IC and a PCB) between the IC and a printed circuit board (PCB) (board 133) to prevent shorting of adjacent solder balls (solder balls 130 are illustrated as having shorting prevented);
producing the BGA spacer (180 exists therefore it must be produced);
placing the BGA spacer on the BGA package among the plurality of solder balls (Figs. 1A and 1B show 180 and 130 coexisting, therefore placed among);
placing the BGA package on the PCB ([0037]: “coupled to a circuit board 133”) wherein the PCB has a plurality of connection pads (132) corresponding to the plurality of solder balls; and
performing solder processing of the BGA package, and PCB ([0045]: “solder balls”. Fig. 1A shows the solder processing has been completed).
Illustrated below is are marked and annotated figures of Figs. 1A and 1B of Gowda.
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Regarding claim 11, Gowda discloses the method of claim 9 (Fig. 1A), further comprising characterizing warpage characteristics of the PCB ([0037]: “simulation… the combination of the IC package coupled to a circuit board”), wherein determining the location of the BGA spacer is further based on the warpage characteristics of the PCB (the PCB being inclusive within the simulation, therefore location is based at least “on the warpage characteristics of the PCB”).
Regarding claim 12, Gowda discloses the method of claim 9 (Fig. 1A), further comprising producing a custom installation template (the locations of spacers 180 appears deliberate, therefore the “template” is whatever set of instructions were followed and including the resultant placement these spacers), wherein placing the BGA spacer on the BGA package includes using the custom installation template (the locations of spacers 180 appear deliberate, thus they used the template).
Regarding claim 17, Gowda discloses the method of claim 12 (Fig. 1B), wherein the installation template has a shape (generally the template includes a rectangular arrangement of spacers 180) that matches the IC associated with the installation template (IC 114-1 also has a rectangular shape, and therefore “matches”).
Regarding claim 18, Gowda discloses the method of claim 17 (Fig. 1B), wherein the installation template includes an alignment notch (See annotated figure. The notch is aligned in the X-axis with IC 114-1. Thus, it is an alignment notch).
Regarding independent claim 13 as noted in the 112(b) rejection, Gowda discloses a method of assembling a circuit assembly (Fig. 1A), comprising:
characterizing warpage characteristics ([0037]: “may depend on a degree of counter warpage/balance needed to cancel or minimize warpage”) of an integrated circuit (IC) (114-1) with a plurality of connection pads (124);
determining locations of a plurality of ball grid array (BGA) spacers (180; [0037]: “determined”) among a plurality of solder balls (130, a plurality is arranged in an array as shown in Fig. 1B) that are part of a BGA package (102. Note: 102 contains several distinct structures combined as a single unit, i.e. the wirings and layers described in [0042]; thus, it is a package) attached to the IC based upon the warpage characteristics of the IC ([0037]: “to cancel or minimize warpage”);
determining a shape and dimensions of the plurality of BGA spacers based upon a height and spacing of the plurality of solder balls ([0037]: “a height (e.g., z-direction or a thickness) of the stiffener 180 may be between 20% and 80% of a second level interconnect 130 height”. Note: the BGA spacer 180 is located within the solder ball spacing),
wherein a height of the plurality of BGA spacers is further based upon a minimum distance (See annotated figure 1A. This distance is vertically between the IC and a PCB) between the IC and a printed circuit board (PCB) (board 133) to prevent shorting of adjacent solder balls (solder balls 130 are illustrated as having shorting prevented);
producing the plurality of BGA spacers (180 exists therefore they must be produced);
placing the plurality of BGA spacers on the BGA package among the plurality of solder balls (Figs. 1A and 1B show 180 and 130 coexisting, therefore placed among);
placing the BGA and IC on the PCB ([0037]: “coupled to a circuit board 133”) wherein the PCB has a plurality of connection pads (132) corresponding to the plurality of solder balls; and
perform solder processing of the IC, BGA package, and PCB ([0045]: “solder balls”. Fig. 1A shows the solder processing has been completed).
Regarding claim 15, Gowda discloses the method of claim 13 (Fig. 1A), further comprising characterizing warpage characteristics of the PCB ([0037]: “simulation… the combination of the IC package coupled to a circuit board”), wherein determining the location of the plurality of BGA spacers is further based on the warpage characteristics of the PCB (the PCB being inclusive within the simulation, therefore location is based at least “on the warpage characteristics of the PCB”).
Regarding claim 16 as noted in the 112(b) rejection, Gowda discloses the method of claim 13, further comprising producing a custom installation template (the locations of spacers 180 appears deliberate, therefore the “template” is whatever set of instructions were followed and including the resultant placement these spacers), wherein placing the plurality of BGA spacers on the BGA package includes using the custom installation template (the locations of spacers 180 appear deliberate, thus they used the template).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Gowda as applied to claim 9 above, and further in view of Liao.
Regarding claim 10, Gowda discloses the method of claim 9 (Fig. 1A), however, fails to teach “wherein determining the location of the BGA spacer includes identifying a location where a distance between the IC and the PCB is less than a minimum distance between the IC and the PCB to prevent shorting of adjacent solder balls”.
Liao discloses a method in the same field of endeavor (Fig. 18), wherein determining the location of the BGA spacer (270) includes identifying a location where a distance between the IC and the PCB is less than a minimum distance (See annotated figure. This distance is vertically between the IC and the PCB) between the IC (900) and the PCB (100) to prevent shorting of adjacent solder balls (the solder balls are illustrated as having shorting prevented, i.e., none are directly shorted; [0044]: “may eliminate or reduce bumps-joint bridges”).
Modifying the method of Gowda by including the method step of Liao would arrive at the claimed method. Liao provides a teaching to motivate one to include the method step in that it would improve manufacturing yield ([0044]: “so as to improve joint formation process window for package manufacture processes”). Therefore, it would have been obvious to have the claimed method configuration because it would improve manufacturing yield. MPEP 2143 (I)(G).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Gowda as applied to claim 13 above, and further in view of Liao.
Regarding claim 14, Gowda discloses the method of claim 13 (Fig. 1A), however, fails to teach “wherein determining the location of the plurality of BGA spacers includes identifying locations where a distance between the IC and the PCB are less than a minimum distance between the IC and the PCB to prevent shorting of adjacent solder balls”.
Liao discloses a method in the same field of endeavor (Fig. 18), wherein determining the location of the plurality of BGA spacers (270) includes identifying a location where a distance between the IC (900) and the PCB (200) are less than a minimum distance (See annotated figure. This distance is vertically between the IC and the PCB) between the IC and the PCB to prevent shorting of adjacent solder balls (the solder balls are illustrated as having shorting prevented, i.e., none are directly shorted; [0044]: “may eliminate or reduce bumps-joint bridges”).
Modifying the method of Gowda by including the method step of Liao would arrive at the claimed method. Liao provides a teaching to motivate one to include the method step in that it would improve manufacturing yield ([0044]: “so as to improve joint formation process window for package manufacture processes”). Therefore, it would have been obvious to have the claimed method configuration because it would improve manufacturing yield. MPEP 2143 (I)(G).
Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but they are not persuasive.
Applicant argues:
Applicant argues “it appears that the publication number “2016/0066426” for the Liao reference, which is found in the Office Action at page 5, appears to be incorrect…In view of the foregoing, Applicant's responses to the art-based rejections that cite Liao are based on the content of the Office Action (exclusive of the erroneous publication number) and the content of the US Patent Application Publication 2023/0352381 to Li-Ling Liao, et al”.
Examiner’s reply:
The examiner agrees with Applicant’s remarks and finds the responses directed to the correct prior art.
Applicant argues:
Applicant argues with respect to amended claim 1 that “Liao's buffer block structures are disposed between the chip and the chip-side of the BGA package. This is a different arrangement than is specified by amended independent claim 1”. Remarks at pg. 10.
Examiner’s reply:
The examiner disagrees and finds the structures (i.e., “BGA package”) and spatial arrangements as claimed reasonably including structures and arrangements beyond the explicit teachings in Applicant’s disclosure. MPEP 2111.
Applicant argues:
Applicant argues with respect to amended claims 9 and 13 that “There is no mention in Gowda of solder bridging, solder ball shorting, or the claimed minimum spacing”. Remarks at pg. 12.
Examiner’s reply:
The examiner disagrees because Gowda does not teach shorting in the drawings or disclosure, thus, in at least the circumstances explicitly illustrated, shorting is prevented. The examiner points to MPEP 2112 for guidance regarding additional circumstances beyond those explicitly illustrated and cited. Applicant has not provided a sufficient showing that the structures disclosed by Gowda would not possess the contended characteristic and the examiner points to MPEP 2145 (I) and (II) for guidance why Applicant’s remarks are unpersuasive.
Applicant argues:
Applicant argues with respect to claim 10 that “Liao’s buffer block structure 270 is not a BGA spacer. Rather, Liao’s buffer block structure 270 is disposed between a chip and the chip-side of a BGA package”. Remarks at pg. 13.
Examiner’s reply:
The examiner disagrees because Gowda and Liao each disclose the spacer among a grid of solder balls (Gowda: Fig. 1A: spacer 180, balls 130; Liao: spacer 270: balls 290). Regardless of which grid of solder balls the spacer is arranged with, the function would be the same because the structure of the spacer is the same in each situation, i.e., a solid block of material configured among solder balls. Thus, the teachings of Liao are relevant to the structures of Gowda. Furthermore, the examiner finds Liao teaching yield related specifically to short-prevention among solder balls (Gowda: [0044]: “The buffer block structures may eliminate or reduce bumps-joint bridges so as to improve joint formation process window for package manufacture processes”. Note: “bridges” is equivalent to shorts based on ordinary and customary usage in the art; “process window” is equivalent to yield based on ordinary and customary usage in the art.). Accordingly, the examiner maintains rejection of the claim for similar reasons as before.
Applicant argues:
Applicant argues with respect to claim 14 that “Liao merely describes the yield for a package manufacturing process itself, i.e., mounting the chip to the BGA package, and does not address the claimed method of for preventing solder ball shorts”. Remarks at pg. 16.
Examiner’s reply:
The examiner disagrees because Gowda and Liao each disclose the spacer among a grid of solder balls (Gowda: Fig. 1A: spacer 180, balls 130; Liao: spacer 270: balls 290). Regardless of which grid of solder balls the spacer is arranged with, the function would be the same because the structure of the spacer is the same in each situation, i.e., a solid block of material configured among solder balls. Thus, the teachings of Liao are relevant to the structures of Gowda. Furthermore, the examiner finds Liao teaching yield related specifically to short-prevention among solder balls (Gowda: [0044]: “The buffer block structures may eliminate or reduce bumps-joint bridges so as to improve joint formation process window for package manufacture processes”. Note: “bridges” is equivalent to shorts based on ordinary and customary usage in the art; “process window” is equivalent to yield based on ordinary and customary usage in the art.). Accordingly, the examiner maintains rejection of the claim for similar reasons as before.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to WILLIAM H ANDERSON whose telephone number is (571)272-2534. The examiner can normally be reached Monday-Friday, 8:00-5:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Kretelia Graham can be reached at (571) 272-5055. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/WILLIAM H ANDERSON/ Examiner, Art Unit 2817
/Kretelia Graham/ Supervisory Patent Examiner, Art Unit 2817 January 12, 2026