DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I in the reply filed on 11/24/2025 is acknowledged. The traversal is on the ground(s) that there is no search burden and the groups are inextricably linked. This is not found persuasive because the inventions are classified in different groups, and the method claims require separate method steps. Rejoinder issues will be addressed upon the indication of allowable subject matter.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uno et al (EP 2629329A2).
With respect to Claim 1, Uno et al discloses a semiconductor device package (Figures 1A-1B) comprising : a semiconductor die (Figures 1A-1B) having a circuit integrated thereon (paragraph 19); a first clip (Figure 1A-1B, plate wire, 3 and 3a and 3b) comprising a first planar portion (Figure 1B, 3) and one or more first leads (Figures 1A-1B, terminal 6) extending from the first planar portion, the first planar portion comprising one or more first protrusions (Figures 1A-1B, 3a and 3b) ; a second clip (Figure 1A-1B, plate wire, 4 and 4a and 4b ) comprising a second planar portion (Figure 1B, 4) and one or more second leads (Figures 1A-1B, terminal 7) extending from the second planar portion, the second planar portion comprising a plurality of second protrusions (Figures 1A-1B, 4a and 4b); wherein the first planar portion and the second planar portion are each physically and electrically connected to a same terminal of the circuit arranged on the semiconductor die (Figures 1A-1B, 2); wherein at least one of the one or more first protrusions (Figures 1A-1B, 3b) extends in a space between a pair of second protrusions among the plurality of second protrusions (Figures 1A-1B, 4a and 4b) . See Figures 1A-1B, 18 and 22-23, especially paragraphs 18-33.
With respect to Claim 2, Uno et al discloses wherein the one or more first protrusions (Figures 1A-1B, 3a and 3b) are arranged symmetrically along an axis parallel to a direction in which the one or more first protrusions extend; and/or wherein the plurality of second protrusions are arranged symmetrically along an axis parallel to a direction in which the plurality of second protrusions (Figures 1A-1B, 4a and 4b) extend.
With respect to Claim 3, Uno et al wherein the one or more first leads (Figures 1A-1B, terminal 6) extend along an axis parallel to a direction in which the one or more first protrusions (Figures 1A-1B, 3a and 3b) extend; and/or wherein the one or more second leads (Figures 1A-1B, terminal 7) extend along an axis parallel to a direction in which the plurality of second protrusions extend (Figures 1A-1B, 4a and 4b) ; and/or wherein the one or more first protrusions extend (Figures 1A-1B, 3a and 3b)in a direction opposite to a direction in which the plurality of second protrusions extend (Figures 1A-1B, 4a and 4b).
With respect to Claim 4, Uno et al discloses wherein the first planar portion and the second planar portion each cover at least 20% of a surface of the semiconductor die on which they are arranged; and/or wherein the first planar portion (Figures 1A-1B, 3) and the second planar portion (Figures 1A-1B, 4) are spaced apart on the semiconductor die, wherein the semiconductor die has an uncovered portion of a surface not covered by the first and second planar portion that forms a meandering line, wherein the uncovered portion extends from a first edge of the surface of the semiconductor die to a second edge of the surface, the second edge being opposite the first edge. See Figures 1A-1B and corresponding text.
With respect to Claim 5, Uno et al discloses further comprising a die pad (Figure 1A, 11) on which the semiconductor die (Figure 1A, 2) is arranged, wherein the die pad is electrically conductive, wherein the circuit comprises a further terminal electrically connected to the die pad, and wherein the die pad has a surface that is exposed to an outside of the semiconductor device package (Figure 23) . See paragraphs 18-24.
With respect to Claim 6, Uno et al wherein the semiconductor device package further comprises a contact comprising a contact portion physically and electrically connected to a gate terminal of the FET, and one or more third leads extending from the contact portion (Figure 3) ; and a body of solidified molding compound (paragraph 124, 46 and Figure 23) encapsulating the semiconductor die, the first planar portion, the second planar portion and the contact portion, wherein the one or more first leads, the one or more second leads and the one or more third leads are at least partially arranged externally to the body of solidified molding compound (Figure 23). See Figure 23 and corresponding text.
With respect to Claim 7, Uno et al discloses the leads extend along an axis parallel to a direction of the corresponding protrusions. See Figures 1A and 1B.
With respect to Claim 8, Uno et al discloses the circuit comprises a FET connection as required by Claim 8. See Figures 2A, 2B and 3 and corresponding text.
With respect to Claim 9, Claim 9 is rejected for the reasons as discussed above with respect to Claim 1. The providing and arranging the components are inherent to the disclosure of the limitations of Claim 1.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALEXANDER G GHYKA whose telephone number is (571)272-1669. The examiner can normally be reached Monday-Friday 9-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine Kim can be reached at 571 272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
AGG
January 15, 2026
/ALEXANDER G GHYKA/Primary Examiner, Art Unit 2812