Prosecution Insights
Last updated: July 17, 2026
Application No. 18/298,906

ROW REPAIR AND ACCURACY IMPROVEMENTS IN ANALOG COMPUTE-IN-MEMORY ARCHITECTURES

Non-Final OA §102§103§112
Filed
Apr 11, 2023
Examiner
KING, DOUGLAS
Art Unit
Tech Center
Assignee
Intel Corporation
OA Round
1 (Non-Final)
80%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
84%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
591 granted / 739 resolved
+20.0% vs TC avg
Minimal +4% lift
Without
With
+4.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
20 currently pending
Career history
757
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
73.7%
+33.7% vs TC avg
§102
15.7%
-24.3% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 739 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement Acknowledgment is made of applicant's Information Disclosure Statement (IDS) Form PTO-1449. The information disclosed therein was considered. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites “the instructions, when executed…” which lacks antecedent basis or scope definition for clarity as this appears to be an error. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 6 and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim (US 2022/0398037). Regarding claim 1, Sun discloses a computing system comprising (See Figures 1-4): a network controller; and a processor coupled to the network controller, the processor including one or more substrates (see paragraph 0044) and logic coupled to the one or more substrates, the logic including: a plurality of analog to digital converters (see Figure 3A, ADC’s), compute-in-memory multiply-accumulate hardware (array, S&H, etc.) coupled to the plurality of ADCs, and a plurality of digital to analog converters (DAC 304a-c for example) coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs (DAC 304d). Regarding claim 6, Sun discloses an apparatus comprising: one or more substrates; and logic coupled to the one or more substrates (see rejection of claim 1 above), wherein the logic is implemented at least partly in one or more of configurable or fixed-functionality hardware (see paragraph 0037), the logic including: a plurality of analog to digital converters ; compute-in-memory multiply-accumulate hardware coupled to the plurality of ADCs; and a plurality of digital to analog converters coupled to the CiM MAC hardware, wherein the plurality of DACs includes one or more redundant DACs (see rejection of claim 1 above). Regarding claim 13, Sun discloses the apparatus of claim 6, wherein the logic coupled to the one or more substrates includes transistor regions that are positioned within the one or more substrates (see paragraph 0044). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 2, 3, 7, 8, 11, 12, 14, 15, 19-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Toshiaki (US 5,555,212). Regarding claim 14, 2 and 7, Sun discloses at least one computer readable storage medium comprising a set of instructions, which when executed by a computing system, cause the computing system to (see paragraph 0161): detect a defect in compute-in-memory multiply-accumulate hardware (see clause 15 for example), wherein the CiM MAC hardware is coupled to a plurality of analog to digital converters and a plurality of digital to analog converters , and wherein the plurality of DACs includes one or more redundant DACs; disconnect an affected DAC in the plurality of DACs (see rejection of claim 1 above). Sun fails to teach wherein the affected DAC is associated with a row corresponding to the defect; activate at least one of the one or more redundant DACs; and remap inputs of the affected DAC to the at least one of the one or more redundant DACs. That is, Sun fails to teach that faulty row circuitry is replaced and it’s input remapped to a second row circuit. But type of fault correction was known at the time of filing. For example, Toshiaka (see Figure 5, shows redundant row drive circuitry which replaces faulty row circuitry—having the failed row inputs remapped to the replacement row circuits via RRDN). Therefore, it would have been obvious to one having ordinary skill at the time of filing to remap failed row circuits to good row circuits as outlined by Toshiaka in order to reduce errors in the device. Regarding claim 15, 3 and 8, Sun discloses the at least one computer readable storage medium of claim 14, wherein the affected DAC is disconnected via one or more of a plurality of switches (word line drivers contain switches—transistors and logic gates). Regarding claim 19 and 11, Sun discloses the at least one computer readable storage medium of claim 14, wherein the defect is detected with respect to a bitcell in the CiM MAC hardware (cell storage errors are in the bit cell). Regarding claim 20 and 12, Sun discloses the at least one computer readable storage medium of claim 14, wherein the defect is detected with respect to a capacitance in the CiM MAC hardware (an error Allowable Subject Matter Claims 4, 9, 10, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Regarding claim 16, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including wherein the plurality of switches are to be positioned between capacitors in the CiM MAC hardware and the plurality of ADCs. Regarding claim 17 and 18, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including wherein the instructions, when executed, further cause the computing system to: detect one or more zero-valued input activations; and disconnect one or more DACs corresponding to the one or more zero-valued input activations. Regarding claims 4, 9 and 16, the prior art fails to teach or reasonably disclose in combination all the features of the claim in combination with preceding claim limitations including, wherein the plurality of switches are positioned between capacitors in the CiM MAC hardware and the plurality of ADCs. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The remaining cited and attached references teach various embodiments of row repair and CIM devices. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS KING whose telephone number is (571)272-2311. The examiner can normally be reached M-F: 9:00AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached on 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DOUGLAS KING/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Apr 11, 2023
Application Filed
May 19, 2023
Response after Non-Final Action
Jun 15, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
80%
Grant Probability
84%
With Interview (+4.5%)
2y 6m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 739 resolved cases by this examiner. Grant probability derived from career allowance rate.

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