Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 11/12/2025.
Claims 1-20 are currently pending.
Claim 7 has been withdrawn.
Claims 1-6 and 8-20 have been examined.
Priority
Applicant' s claim for the benefit of a prior-filed application under 35 U.S.C. 119(e) or under 35 U.S.C. 120, 121, 365(c), or 386(c) is acknowledged. The instant application is a continuation and claims priority from U.S. Patent Application No. 16/286,897, filed February 27, 2019, which claims priority under 35 U.S.C. §119 to Korean Patent Application No. 10-2018-0104648, filed September 3, 2018. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restriction
Applicant's election without traverse of claims Species B corresponding to claims 4, 5, 6, and 16, in the reply filed on 11/12/2025, is acknowledged. Claims 1-3, 8-15, and 17-20 are considered to be generic. Claim 7 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species A, there being no allowable generic or linking claim.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 4/12/2023, 6/28/2023, and 2/27/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 112
112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 13-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
To the Examiner’s understanding, there is no explanation of the height of the vertical transfer gate and that is it specifically “longer” than the vertical height of the grating structure within the specification. While the vertical height of the transfer gate must be present, the drawings are schematic and non-limiting (Specification at [0009].). Therefore the drawings cannot be considered to provide support “a vertical height of the vertical transfer gate is longer than a vertical height of the grating structure.” (Emphasis added.)
Claims 14-20 are rejected based on the dependence of the claims to independent claim 13.
112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 15 recites the limitation "the vertical gate electrode" in the first line of the claim. There is insufficient antecedent basis for this limitation in the claim.
For purposes of Examination the claim will be read as “the vertical transfer gate
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 9, 11, and 12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Uesaka US 20190006407 A1 (hereinafter Uesaka).
The following annotated Fig. 2 will be used in discussion of the claims:
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Regarding claim 1, Uesaka discloses:
An image sensor (Fig. 2, a solid-state imaging apparatus.) comprising:
a semiconductor substrate (substrate 102) that has a first surface (annotated Fig. 2, 102a) and a second surface opposite to the first surface; (annotated Fig.2, 102b)
a pixel separation structure that vertically extends from the first surface to the second surface and defines a pixel region; (Through-hole electrode 126, [0059] the through-electrode encloses the side surface of each photoelectric conversion device 122 thereby defining the pixel region.)
a grating structure (Annotated Fig. 2, structure 124_gs including a plurality of polarizers 124.) disposed on the second surface of the semiconductor substrate; and (See Fig. 2 and [0057].)
a read-out circuit layer disposed on the first surface of the semiconductor substrate, (See annotated Fig. 2 and [0053] wiring layer 101 disposed on surface of the substrate 102b.)
wherein a contact surface (Annotated Fig.2, contact surface 102c.) of the read-out circuit layer (wiring layer 1010) and the pixel separation structure (through-hole electrode 126) is located on the first surface (surface of the substrate 102a) of the semiconductor substrate, and
wherein a top surface of the pixel separation structure is lower than a top surface of the grating structure. (See annotated Fig. 2, the top surface of the through-hole electrode 126 is considered to be at the same height as the surface of the substrate 102b which is lower than the top surface of the polarizer 124.)
Regarding claim 2, Uesaka further discloses:
wherein the top surface of the grating structure is higher than the second surface of the semiconductor substrate. (See annotated Fig. 2, the top surface of the polarizer 124 is higher than the surface of the substate 102b.)
Regarding claim 3, Uesaka further discloses:
wherein the second surface of the semiconductor substrate is located at substantially the same level as the top surface of the pixel separation structure. (See annotated Fig. 2, the surface of substrate 102b is at the same level as the top of the through-hole electrode 126.)
Regarding claim 4, Uesaka further discloses:
wherein the grating structure (annotated Fig. 2, grating structure 124_gs) incudes grating patterns (polarizer 124) and recess regions (annotated Fig. 2, recess regions of the polarizer 124a) alternately arranged, and (See also, [0057].)
wherein the grating patterns (polarizer 124) are protruded from the second surface of the semiconductor substrate. (See annotated Fig. 2, the top surface of the polarizer 124 is protruding from the surface of the substate 102b. See also, [0056].)
Regarding claim 5, Uesaka further discloses:
wherein the top surface of the grating structure corresponds to top surfaces of the grating patterns. (The grating structure 124_gs includes the plurality of polarizers 124. Therefore the top surface of the polarizers is the polarizers 124 is the top surface of the grating structure 124_gs.)
Regarding claim 6, Uesaka further discloses:
wherein top surfaces of the grating patterns are higher than the second surface of the semiconductor substrate. (See annotated Fig. 2, the top surface of the polarizer 124 is higher than the surface of the substate 102b. See also, [0056].)
Regarding claim 9, Uesaka further discloses:
wherein the grating structure(annotated Fig. 2, grating structure 124_gs) comprises grating patterns (polarizer 124) provided on the pixel region(Fig. 3 pixels P, including pixel Pa, Pb, Pc, an Pd.) and arranged in an n x n matrix. (Fig. 3 depicts a plan view of the device of Fig. 2 which shows that the pixels are arranged in an n x n matrix.)
Regarding claim 11, Uesaka further discloses:
wherein the grating structure (annotated Fig. 2, grating structure 124_gs) comprises grating patterns (polarizer 124) each has a rectangular shape when viewed in a plan view. (Fig. 3 depicts the plan view of Fig. 2 and [0057] shows and example arrangement of the polarizer 124, which are depicted as a rectangular shape arranged on the pixels Pa.)
Regarding claim 12, Uesaka further discloses:
wherein the pixel separation structure (through-hole electrode 126) surrounds the pixel region (Fig. 3 pixels P, including pixel Pa, Pb, Pc, an Pd.) when viewed in a plan view. (Fig. 2 shows that the through-hole electrodes 126 are below the through-hole electrode 125 and Fig. 3 shows the plan view and that the through-hole electrodes 125 surround the pixel region. Therefore the through-hole electrodes 126 would surround the pixel region pixel P.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Uesaka as applied to claim 1 above, and further in view of Ahn et al. US 20130307040 A1 (hereinafter Ahn).
The following annotated Figure 3A will be used in discussion:
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Regarding claim 8, Uesaka teaches all the elements of claim 1.
Uesaka discloses a read-out circuit (Fig. 2, wiring layer 101).
Uesaka does appear to specifically disclose that “the read-out circuit (wiring layer 101) layer comprises:
a transistor provided on the first surface of the semiconductor substrate, and
an interlayered insulating layer provided on the first surface of the semiconductor substrate to cover the transistor.”
Ahn, which teaches image sensor has a transfer gate (Ahn, Abstract), discloses:
the read-out circuit layer (Ahn, annotated Fig. 3A, read-out circuit layer 200) comprises:
a transistor (Ahn, [00422], transistor Tx1 which includes transfer gate TG1.) provided on the first surface of the semiconductor substrate (annotated Fig. 3A, first surface of the semiconductor substrate 100a), and (transfer gate TG1 is on the first surface of the first surface of the semiconductor substrate 100a.)
an interlayered insulating layer (interlayer insulating layer DL1) provided on the first surface of the semiconductor substrate to cover the transistor. (interlayer insulating layer DL1 is on the first surface of the first surface of the semiconductor substrate 100a.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uesaka to have read-out circuit layer a transistor provided on the first surface of the semiconductor substrate, and an interlayered insulating layer provided on the first surface of the semiconductor substrate to cover the transistor as taught by Ahn for purposes of effectively transfer the electric field to the photoelectric conversion parts. (Ahn, [0057].)
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Uesaka as applied to claim 1 above, and further in view of Yeh et al. US 20180228410 A1 (hereinafter Yeh).
Regarding claim 10, Uesaka teaches all the elements of claim 1.
Uesaka shows in the plan view of the device in Fig. 3 that would by necessity have some fill factor of the grating structure. However, Uesaka does not specifically show that “the grating structure is designed to have a fill factor of 50%.”
Yeh, which teaches a grating layer and a thin film waveguide to form reflection and transmission filters for particular wavelengths (Yeh, Abstract) discloses that a grating structure is defined by a grating period (Λ) and a fill factor, (f). (Yeh, [0029].) Furthermore the fill factor may be adjusted to compensate for potential peak shifts that may be caused by other layers. (Yeh, [0031].)
To the extent understood by the Examiner, there is no evidence of criticality of a fill factor of 50% in the specification. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uesaka to have the grating structure is designed to have a fill factor of 50% as taught by Yeh for purposes of adjusting the grating structure to partially reflect and partially transmit light. (Yeh, [0029].)
Claims 13-18, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn in view of Uesaka.
Regarding claim 13, Ahn discloses:
An image sensor (Ahn, Abstract, Fig.3A) comprising:
a semiconductor substrate (annotated Fig. 3A, substrate 100) that has a first surface (first surface 100a) and a second surface opposite to the first surface; (second surface 100b)
a pixel separation structure (deep device isolation layer DTI) that vertically extends from the first surface to the second surface and defines a pixel region; (Fig. 3A, [0049])
…
a vertical transfer gate disposed on the first surface; (Transfer gate TG1, [0052] including the protruding portion 21 that is disposed on the first surface 100a.)
a read-out circuit layer (annotated Fig. 3A, read-out circuit layer 200) disposed on the first surface; and (Read-out circuit layer 200 is disposed on the first surface 100a.)
wherein a first horizontal cross section (first width DTI_W1) of the pixel separation structure (deep device isolation layer DTI) is wider than a second horizontal cross section (second width DTI_W2) of the pixel separation structure , (The single structure deep device isolation layer DTI is wider at the first width W1 than the second width DTI_W2.)
wherein the first horizontal cross section (first width DTI_W1) is closer to the first surface (first surface 100a) than the second horizontal cross section (second width DTI_W2), and
wherein a vertical height (There is an inherent height of the transfer gate TG1_H) of the vertical transfer gate (transfer gate TG1)…
Ahn does not appear to disclose “a grating structure disposed on the second surface;” or that the vertical heigh transfer gate “is longer than a vertical height of the grating structure.”
Uesaka, which teaches a solid-state imaging apparatus with a polarizer above a photo-electric conversion device (Uesaka, Abstract), discloses:
a grating structure (annotated Fig. 2, structure 124_gs including a plurality of polarizers 124) disposed on the second surface; (second substrate 102b)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ahn to have a grating structure disposed on the second surface as taught by Uesaka. The purpose is lowering the upper layer of the photoelectric conversion device and enhancing the sensitivity of the device. (Uesaka, [0056].)
One of ordinary skill in the art would recognize that the combination of the device of Ahn and Uesaka would necessarily result in a device that has the vertical height of the transfer gate being longer than the vertical height of the grating structure. The combination of Ahn and Uesaka would result in a device which places the grating structure on the top surface of substrate below the color filter layer and microlens. Uesaka’s grating structure is formed inside same layer at the oxide film 123 and is underneath the color filter 128 and microlens 129. See Uesaka Fig. 2. Ahn’s protective film 30 is a metal oxide, therefore being a oxide film, on which the color filter CF1 and CF2 and microlens ML sits. See Ahn Fig. 3A. Therefore the grating structure would be in the protective layer 30 of Ahn. Furthermore, Ahn Fig. 3A also shows the inherent relative heights of the protective layer 30 of Ahn to the height of the transfer gate TG1_H. The transfer gate height is longer than the height of the protective layer 30 and would by necessity be longer than any grating structure that would be within the protective layer 30 of Ahn.
Regarding claim 14, Ahn as modified by Uesaka discloses all the elements of claim 13.
Uesaka further discloses:
wherein the vertical height of the grating structure is a vertical length measured from the second surface of the semiconductor substrate to a top surface of the grating structure. (See annotated Fig. 2, the top surface of the polarizer 124 is measured from the surface of the substate 102b.)
Regarding claim 15, Ahn as modified by Uesaka discloses all the elements of claim 13.
Ahn further discloses:
wherein the vertical transfer gate (transfer gate TG1) (hole H) recessed from the first surface of the semiconductor substrate (surface of the substrate 100a).
Regarding claim 16, Ahn as modified by Uesaka discloses all the elements of claim 13.
Uesaka further disclose:
wherein the grating structure (annotated Fig. 2, grating structure 124_gs) comprises grating patterns (polarizer 124) and recess regions (annotated Fig. 2, recess regions of the polarizer 124a) alternately arranged, (See also, [0057].)
wherein the grating patterns (polarizer 124) are protruded from the second surface of the semiconductor substrate. (See annotated Fig. 2, the top surface of the polarizer 124 is protruding from the surface of the substate 102b. See also, [0056].)
Regarding claim 17, Ahn as modified by Uesaka discloses all the elements of claim 13.
Uesaka further discloses:
wherein the grating structure(annotated Fig. 2, grating structure 124_gs) comprises grating patterns (polarizer 124) provided on the pixel region(Fig. 3 pixels P, including pixel Pa, Pb, Pc, an Pd.) and arranged in an n x n matrix. (Fig. 3 depicts a plan view of the device of Fig. 2 which shows that the pixels are arranged in an n x n matrix.)
Regarding claim 18, Ahn as modified by Uesaka discloses all the elements of claim 17.
Uesaka further discloses:
wherein the pixel separation structure (through-hole electrode 126) surrounds the pixel region (Fig. 3 pixels P, including pixel Pa, Pb, Pc, an Pd.) when viewed in a plan view. (Fig. 2 shows that the through-hole electrodes 126 are below the through-hole electrode 125 and Fig. 3 shows the plan view and that the through-hole electrodes 125 surround the pixel region. Therefore the through-hole electrodes 126 would surround the pixel region pixel P.)
Regarding claim 20, Ahn as modified by Uesaka discloses all the elements of claim 13.
Uesaka further discloses:
wherein the grating structure (annotated Fig. 2, grating structure 124_gs) comprises grating patterns (polarizer 124) each has a rectangular shape when viewed in a plan view. (Fig. 3 depicts the plan view of Fig. 2 and [0057] shows and example arrangement of the polarizer 124, which are depicted as a rectangular shape arranged on the pixels Pa.)
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Ahn and Uesaka as applied to claim 13 above, and further in view of Yeh.
Regarding claim 19, Ahn as modified by Uesaka discloses all the elements of Claim 13.
Uesaka shows in the plan view of the device in Fig. 3 that would by necessity have some fill factor of the grating structure. However, Uesaka does not specifically show that “the grating structure is designed to have a fill factor of 50%.”
Yeh, which teaches a grating layer and a thin film waveguide to form reflection and transmission filters for particular wavelengths (Yeh, Abstract) discloses that a grating structure is defined by a grating period (Λ) and a fill factor, (f). (Yeh, [0029].) Furthermore the fill factor may be adjusted to compensate for potential peak shifts that may be caused by other layers. (Yeh, [0031].)
To the extent understood by the Examiner, there is no evidence of criticality of a fill factor of 50% in the specification. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Uesaka to have the grating structure is designed to have a fill factor of 50% as taught by Yeh for purposes of adjusting the grating structure to partially reflect and partially transmit light. (Yeh, [0029].)
Prior Art Made of Record
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Honda US 20180302597 A1 – Fig. 2, shows an image capturing device with a polarization layer.
Wang US 20180259691 A1 – the grating layer arranged inside the display panel.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, DAVIENNE MONBLEAU can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/HEIM KIRIN GREWAL/ Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/ Supervisory Patent Examiner, Art Unit 2812