Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 5/29/2026.
Claims 1-20 are currently pending.
Claims 7 have been withdrawn.
Claims 1, and 13-16 have been amended.
Claims 1-6 and 8-20 have been examined.
Response to Applicants Amendments
The amendments to claims 13 and 15 overcome the rejections under 112(a) and 112(b). Therefore the rejection under 35 U.S.C §112 are withdrawn in relation to claims 13-20 and claim 15 respectively.
Applicant’s arguments, see page 7, filed 5/29/2026, with respect to the rejection(s) of claim 1-6, 9, 11, and 12 and in particular to claim 1 under 102 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Ahn US 20130307040 A1 and Yang - US 20070298533 A1. See below for further details.
Applicant’s arguments, see page 8, filed 5/29/2026, with respect to claim 13-18 and 20 and in particular claim 13 have been fully considered and are persuasive. The rejection of 3/3/2026 has been withdrawn and the claims are found in condition for allowance. See below for further details.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-6 and 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ahn et al. US 20130307040 A1 (hereinafter Ahn) and Yang et al. US 20070298533 A1 (hereinafter Yang).
The following annotated figure will be used in discussion:
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Regarding claim 1, Ahn discloses:
An image sensor (Ahn, Abstract, Fig.3A) comprising:
a semiconductor substrate (annotated Fig. 3A, substrate 100) that has a first surface (first surface 100a) and a second surface opposite to the first surface; (second surface 100b)
a pixel separation structure (deep device isolation layer DTI) that vertically extends from the first surface to the second surface and defines a pixel region; (Fig. 3A, [0049])
…
a read-out circuit layer (annotated Fig. 3A, read-out circuit layer 200) disposed on the first surface; and (Read-out circuit layer 200 is disposed on the first surface 100a.)
wherein a contact surface of the read-out circuit layer (read-out circuit layer 200 has a surface 200a) and the pixel separation structure (deep device isolation layer DTI has a surface DTIa) is located on the first surface of the semiconductor substrate. (first surface 100a) (See Fig, 3A.)
Ahn does not appear to disclose:
a grating structure disposed on the second surface of the semiconductor substrate, or
a top surface of the pixel separation structure is lower than a top surface of the grating structure such that the grating structure is disposed higher than the pixel separation structure.
Yang, which teaches imager pixel array employs a grating layer, discloses:
a grating structure (Yang, Fig. 1a, grating structure 112) disposed on the second surface of the semiconductor substrate (Fig. 1a, disposed on the dielectric layer 108); and
a top surface of the pixel separation structure is lower than a top surface of the grating structure (Fig. 3a which can be used with the description of Fig. 1a, the pixel cells 106a, have a separation and that is lower than the top of grating structure.) such that the grating structure is disposed higher than the pixel separation structure. (Fig. 1a, the grating structure is disposed higher than the pixel cell and semiconductor substrate but below microlens 114 and a spacing layer 116. Therefore it would by necessity be higher than any pixel separation structure.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ahn to have a grating structure disposed on the second surface of the semiconductor substrate and a top surface of the pixel separation structure is lower than a top surface of the grating structure such that the grating structure is disposed higher than the pixel separation structure as taught by Yang for purposes of more efficiently and effectively separating and detecting spectral components of incident light to improve the quantum efficiency of imagers. (Yang, [0006].)
Regarding claim 2, Ahn and Yang disclose all the elements of claim 1.
Yang further discloses:
the top surface of the grating structure is higher than the second surface of the semiconductor substrate. (Yang, Fig. 1a, the grating structure the grating structure is higher than the top the dielectric layer 108.)
Regarding claim 3, Ahn and Yang disclose all the elements of claim 1.
Ahn further discloses:
the second surface (Ahn, Fig 3A, second surface 100b) of the semiconductor substrate is located at substantially the same level as the top surface of the pixel separation structure. (Fig. 3A, deep device isolation layer DTI has a top surface that is the same height of the second surface 100b.)
Regarding claim 4, Ahn and Yang disclose all the elements of claim 1.
Yang further discloses:
wherein the grating structure (Yang, grating structure 112) incudes grating patterns (Fig. 1a, grating layer 112a) and recess regions (filling portions 112f where the material of 112a is not present) alternately arranged, and (See, Fig. 1a.)
wherein the grating patterns are protruded from the second surface of the semiconductor substrate. (Fig. 1a, the grating pattern made of the grating layer 112a and filling portion 112f protrude from the dielectric layer 108.)
Regarding claim 5, Ahn and Yang disclose all the elements of claim 4.
Yang further discloses:
the top surface of the grating structure (Yang, grating structure 112) corresponds to top surfaces of the grating patterns. (Fig. 1a, the top of 112a corresponds with grating structure 112.)
Regarding claim 6, Ahn and Yang disclose all the elements of claim 4.
Yang further discloses:
top surfaces of the grating patterns are higher than the second surface of the semiconductor substrate. (Yang, Fig. 1a, grating layer 112a is higher than top of the dielectric layer 108.)
Regarding claim 8, Ahn and Yang disclose all the element of claim 1.
Ahn further discloses:
the read-out circuit layer (Ahn, annotated Fig. 3A, read-out circuit layer 200) comprises:
a transistor ([00422], transistor Tx1 which includes transfer gate TG1.) provided on the first surface of the semiconductor substrate (annotated Fig. 3A, first surface of the semiconductor substrate 100a), and (transfer gate TG1 is on the first surface of the first surface of the semiconductor substrate 100a.)
an interlayered insulating layer (interlayer insulating layer DL1) provided on the first surface of the semiconductor substrate to cover the transistor. (interlayer insulating layer DL1 is on the first surface of the first surface of the semiconductor substrate 100a.)
Regarding claim 9, Ahn and Yang disclose all the element of claim 1.
Yang further discloses:
the grating structure comprises grating patterns provided on the pixel region and arranged in an n x n matrix. (Yang, Fig. 1f show that that the grating layer 112 can be formed in a nxn matrix.)
Regarding claim 10, Ahn and Yang teaches all the elements of claim 1.
Yang further discloses:
the grating structure is designed to have a fill factor of 50%. (Yang, [0037], duty cycle which is the ratio of the grating portion width to the grating period P can range from 30% to 70%.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to would have at once envisaged the claimed fill factor of 50% within the range of 30% to 70%. See MPEP 2131.02 III.
Regarding claim 11, Ahn and Yang disclose all the element of claim 1.
Yang further discloses:
the grating structure comprises grating patterns each has a rectangular shape when viewed in a plan view. (Fig. 1f shows that the grating pattern 112f would be in rectangular in plan view.)
Regarding claim 12, Ahn and Yang disclose all the element of claim 1.
Ahn further discloses:
wherein the pixel separation structure (deep device isolation layer DTI) surrounds the pixel region when viewed in a plan view. (Fig. 2 shows the plan view of the device of Fig. 3, the DTI surrounds the pixel region of the as defined by first pixel UP1 and UP2. )
Allowable Subject Matter
Claims 13-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 13, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, an image sensor comprising "a vertical height of the portion of the vertical transfer gate is longer than a vertical height of the grating structure.".
A combination of Ahn and Yang discloses the following of claim 13,
Regarding claim 13, Ahn discloses:
An image sensor (Ahn, Abstract, Fig.3A) comprising:
a semiconductor substrate (annotated Fig. 3A, substrate 100) that has a first surface (first surface 100a) and a second surface opposite to the first surface; (second surface 100b)
a pixel separation structure (deep device isolation layer DTI) that vertically extends from the first surface to the second surface and defines a pixel region; (Fig. 3A, [0049])
…
a vertical transfer gate disposed on the first surface, (Transfer gate TG1), the vertical transfer gate having a portion that extends from the first surface towards the second surface; (Transfer gate TG1, [0052] including the buried portion 21 that extends downwards towards the second surface 100b.)
a read-out circuit layer (annotated Fig. 3A, read-out circuit layer 200) disposed on the first surface; and (Read-out circuit layer 200 is disposed on the first surface 100a.)
wherein a first horizontal cross section (first width DTI_W1) of the pixel separation structure (deep device isolation layer DTI) is wider than a second horizontal cross section (second width DTI_W2) of the pixel separation structure , (The single structure deep device isolation layer DTI is wider at the first width W1 than the second width DTI_W2.)
wherein the first horizontal cross section (first width DTI_W1) is closer to the first surface (first surface 100a) than the second horizontal cross section (second width DTI_W2), and
wherein a vertical height (There is an inherent height of the transfer gate TG1_H) of the portion of the vertical transfer gate (transfer gate TG1)…
Ahn does not appear to disclose “a grating structure disposed on the second surface,” or that the vertical height “of the portion of the vertical transfer gate is longer than a vertical height of the grating structure.”
Yang, which teaches imager pixel array employs a grating layer, discloses:
a grating structure (Yang, Fig. 1a, grating structure 112) disposed on the second surface of the semiconductor substrate (Fig. 1a, disposed on the dielectric layer 108);
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Ahn to have a grating structure disposed on the second surface of the semiconductor substrate as taught by Yang for purposes of more efficiently and effectively separating and detecting spectral components of incident light to improve the quantum efficiency of imagers. (Yang, [0006].)
However, neither Ahn or Yang teach or disclose an image sensor comprising "a vertical height of the portion of the vertical transfer gate is longer than a vertical height of the grating structure." Yang at most discloses that “the grating structure can have different grating height, periods, and/or duty cycles” (Yang, [0029].) Ahn does not disclose a particular vertical height of the vertical transfer gate. At most Ahn discloses that the width of the buried portion 22 having a width of 100 nm. (Ahn, [0057].)
Claims 14-20 are allowable based of their dependence to independent claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Prior Art Considered Pertinent
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sze et al. US 20200176500 A1 – Fig. 2, [0082] - the height of the individual transfer gate electrodes 112 is in a trench which is 250-450 nm deep which would imply and implicate height to any electrode deposited within that trench to be at most that deep.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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