DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-10 are presented for examination.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show subject matter of claim 1, namely “forming a gate dielectric and a gate conductor on the oxide layer in the trench, wherein the gate dielectric layer is located on an upper-portion side wall of the trench and separates the gate conductor from the semiconductor structure” as described in the specification. Currently, Figure 3g only shows a gate conductor G/133 being formed on the oxide layer 132 without a gate dielectric separating the gate conductor G/133 from the semiconductor structure 111. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim 2 is objected to because of the following informalities: in line 1, "wherein step" should be amended to read -wherein the step-. Appropriate correction is required.
Claim 3 is objected to because of the following informalities: in line 1, "before step of forming a shielding" should be amended to read -before the step of forming the shielding-. Appropriate correction is required.
Claim 4 is objected to because of the following informalities: in line 1, “wherein step” should be amended to read -wherein the step-. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “depositing an oxide layer from above the trench” in line 11. It is unclear what is meant by depositing “from above the trench”. Examiner interprets that “from above the trench” means –on an upper portion of the trench–. Claims 2-10 inherit the deficiencies of claim 1. Appropriate correction is required.
Claim 1 recites “forming a body region, a source region and a drain electrode based on the semiconductor structure.” It is unclear what forming “based on the semiconductor structure” means. Examiner interprets “forming a body region, a source region and a drain electrode based on the semiconductor structure” to mean –forming a body region and a source region in the semiconductor structure and a drain electrode on a back surface of the semiconductor structure–. Claims 2-10 inherit the deficiencies of claim 1. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 2, 4, 5, and 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Probst (US 2012/0235229 and Probst hereinafter) in view of Ding et al (US 2016/0043192 and Ding hereinafter).
As to claims 1, 2, 4, 5, and 7-10: Probst discloses [claim 1] a method for manufacturing a trench-type MOSFET (Figs. 1 and 2A-2H), comprising: providing a semiconductor structure (Fig. 2A; comprising 204 and a substrate under 204; [0032]-[0033]), depositing a mask (masking; [0032]) and performing etching (silicon etch processing techniques; [0032]) to form a trench (210; [0032]) extending from an upper surface (top surface) of the semiconductor structure (comprising 204 and a substrate under 204) to an interior of the semiconductor structure (comprising 204 and a substrate under 204); forming a side oxide layer (Fig. 2A; Probst states that the oxide 230 can be a combination of a thermally formed oxide and a deposited oxide; the side oxide layer is interpreted to be the outer half of 230/thermally formed portion; [0034]) and a dielectric layer (Probst states that the oxide 230 can be a combination of a thermally formed oxide and a deposited oxide; the dielectric layer is interpreted to be the inner half of 230/deposited oxide portion; [0034]) in the trench (210); forming a shielding conductor (Fig 2A; 220; [0035]) in the trench (210), wherein the side oxide layer (outer half of 230/thermally formed portion) and the dielectric layer (inner half of 230/deposited oxide portion) separate the shielding conductor (220) from the semiconductor structure (comprising 204 and a substrate under 204); removing the mask (Fig. 2A; the mask is removed as no mask is shown; [0032]); performing wet etching (Fig. 2B; wet buffered oxide etch; [0036]) to remove a portion (upper portion), which is located at an upper portion of the trench (210), of the side oxide layer (outer half of 230/thermally formed portion) and the dielectric layer (inner half of 230/deposited oxide portion); depositing an oxide layer (Figs. 2C-2D; comprising 232 and 234; [0037]-[0043]) from above the trench (upper portion of trench 210), wherein the oxide layer (comprising 232 and 234) covers the side oxide layer (outer half of 230/thermally formed portion) and dielectric layer (inner half of 230/deposited oxide portion), and the oxide layer (comprising 232 and 234) is adjacent to the shielding conductor (220); etching (Fig. 2E; etching process; [0044]) the oxide layer (comprising 232 and 234) so as to make an upper surface (top surface) of the oxide layer (comprising 232 and 234) lower (etching lowers the top surface from the upper portion of the trench to the mid portion of the trench); forming a gate dielectric layer (Fig. 2F; 236; [0052]) and a gate conductor (Fig. 2G; 240; [0054]) on the oxide layer (comprising 232 and 234) in the trench (210), wherein the gate dielectric layer (236) is located on an upper-portion side wall of the trench (210) and separates the gate conductor (240) from the semiconductor structure (comprising 204 and a substrate under 204); and forming a body region (Fig. 1; body region; [0055]), a source region (Fig. 1; source region; [0055]) and a drain electrode (Fig. 1; drain; [0058]) based on the semiconductor structure (comprising 204 and a substrate under 204); [claim 2] wherein step of forming the side oxide layer in the trench comprises: forming the side oxide layer by thermal oxidation and forming the dielectric layer by chemical vapor deposition (Probst states that the oxide 230 can be a combination of a thermally formed oxide and a deposited oxide; the side oxide layer is interpreted to be the outer half of 230/thermally formed portion and the dielectric layer is interpreted to be the inner half of 230/deposited oxide portion; [0034]); [claim 5] wherein the semiconductor structure (comprising 204 and a substrate under 204) comprises a semiconductor substrate layer (substrate under 204; [0033]) and an epitaxial semiconductor layer (204; [0033]) on the semiconductor substrate layer (substrate under 204), wherein the trench (230) is located in the epitaxial semiconductor layer ([0032]); [claim 7] wherein the gate dielectric layer (Fig. 2F; 236; [0052]) is an oxide layer formed by thermal oxidation ([0067]); [claim 8] wherein, the source region (Fig. 1; 166; [0055] and [0019]) is formed in the body region (168; [0055] and [0019]) and is of a first dopant type (n-type; [0019]); the body region (168) is formed in an upper portion, which is adjacent to the trench (Fig. 1; 110; [0019]), of the semiconductor structure (comprising 204 and a substrate under 204) and is of a second dopant type (p-type; [0019]), wherein the second dopant type is opposite to the first dopant type, wherein the first dopant type is one of N type and P type (n-type), and the second dopant type is the other one of N type and P type (p-type); and the drain electrode (Fig. 1; 150; [0020]) is formed on a second surface (bottom surface) of the semiconductor structure (162 and 167; [0020]), and the second surface (bottom surface) and the upper surface (top surface) of the semiconductor structure (162 and 167) are opposite to each other; [claim 10] wherein before forming the source electrode ([0055]-[0058]), the method further comprises: forming, in the body region (Fig. 1; body region 168; [0019] and [0055]), a body contact region (164; [0055] and [0019]) of the second dopant type (p-type; [0019]).
Probst fails to expressly disclose [claim 1] where the mask is a hard mask; [claim 4] wherein step of removing the hard mask comprises: performing chemical mechanical planarization to remove the hard mask; [claim 9] wherein after forming the source region, the method further comprises: forming an interlayer dielectric layer on the source region; and forming a source electrode on the interlayer dielectric layer; [claim 10] forming a conductive channel penetrating through the interlayer dielectric layer and the source region to reach the body contact region, wherein the source electrode is connected to the body contact region via the conductive channel.
Probst discloses a shielded gate MOSFET.
Ding discloses a shielded gate MOSFET [claim 1] where the mask is a hard mask (Fig. 1A; 120 is a hard mask layer; [0009]); [claim 4] wherein step of removing the hard mask (Figs. 1I and 1J; 120 is hard mask; [0017]) comprises: performing chemical mechanical planarization (CMP; [0017]) to remove the hard mask (120); [claim 9] wherein after forming the source region (Fig. 1N; 170; [0019]), the method further comprises: forming an interlayer dielectric layer (Fig. 1O; 190; [0020]) on the source region (170); and forming a source electrode (Fig. 1O; 220; [0023]) on the interlayer dielectric layer (190); [claim 10] forming a conductive channel (Fig. 1O; metal plugs; [0021]) penetrating through the interlayer dielectric layer (190) and the source region (170) to reach the body contact region (body contact region; [0020]), wherein the source electrode (220) is connected to the body contact region (body contact region) via the conductive channel (metal plugs).
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing a hard mask from the two types of known masks (hard mask or photomask) and using the removal method of CMP; if this leads to the anticipated success, in the instant case a material that can protect a substrate surface during etching of a trench and using a well-known technique to completely remove a hard mask layer (i.e., CMP), it is likely the product not of innovation but of ordinary skill.
As to the interlayer dielectric layer and the source electrode on the interlayer dielectric layer, given the teachings of Ding, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Probst by employing the well-known or conventional features of shielded gate MOSFET, such as displayed by Ding, by employing an interlayer dielectric over the shielded gate trench structure and forming the source electrode on the interlayer dielectric in order to electrically insulate the shielded gate structure from the source electrode while allowing connection to the source and body regions of the shielded gate structure.
As to the conductive channel connected extending through the source region to the body contact region, given the teachings of Ding, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Probst by employing the well-known or conventional features of shielded gate MOSFET, such as displayed by Ding, by employing a conductive channel that penetrates through the source region to contact the body contact region and connects to the source electrode in order to provide a better ohmic contact to the shielded gate device ([0020]) and to short the source region and body region to the source electrode ([0023]).
Probst in view of Ding fail to expressly disclose [claim 1] where the oxide layer is etched to make the upper surface lower than an upper surface of the shielding conductor.
Probst discloses in Fig. 2E removing portions of the oxide layer comprising 232 and 234 by etching. Probst discloses in [0044]-[0051] that a person having ordinary skill in the art before the effective filing date of the claimed invention can modify the amount of the two oxides 232 and 234 that is removed depending on the device wanted by the person having ordinary skill in the art and (as well known in the art) the amount of dielectric isolation needed between the shielding conductor 220 and the gate conductor 240.
Therefore, a person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to etch the oxide layer 234 and/or oxide layer 232 such that enough of at least the oxide layer 234 can be etched/removed such that it has a top surface that is below an upper surface of the shielding conductor 220 while maintaining a desired level of isolation between the shielding conductor and the gate conductor.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Probst in view of Ding as applied to claim 1 above, and further in view of Zhou (CN 208655650 and Zhou hereinafter).
Although the method disclosed by Probst in view of Ding shows substantial features of the claimed invention (discussed in paragraph 16 above), it fails to expressly disclose:
wherein before step of forming a shielding conductor in the trench, the method further comprises: after forming the side oxide layer and the dielectric layer, performing a rapid thermal annealing process, and then depositing polysilicon as the shielding conductor.
Probst in view of Ding discloses a shielded gate MOSFET in a trench wherein the gate dielectric and the shielded dielectrics are oxides.
Zhou discloses in [0046] that after forming an oxide in a trench and prior to forming a conductive material on the oxide, the oxide layer can be subjected to a rapid thermal anneal process.
A person having ordinary skill in the art before the effective filing date of the claimed invention would have had it within their ordinary capabilities to apply the technique of subjecting the side oxide layer and the dielectric layer (which is an oxide) of Probst in view of Ding to a rapid thermal anneal process prior to the formation of the shielding conductor as the technique of improving oxide dielectrics in a trench prior to conductor formation was well known in the art and the application of which would have resulted in the predictable and desirable results of improving the quality of the side oxide layer and dielectric layer as the technique was known to do in the teachings of Zhou ([0046]).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Probst in view of Ding as applied to claim 1 above, and further in view of Xiao et al (CN 114005756 and Xiao hereinafter; a machine translation is used as an English language equivalent).
Probst combined with Ding discloses wherein the shielding conductor (Fig. 2G; 220) and the gate conductor (240) are respectively polysilicon layers ([0035] and [0054]).
Probst in view of Ding fail to expressly disclose where the polysilicon is formed by low-pressure chemical vapor deposition.
Xiao discloses in [0045] and [0057] that shielding and gate polysilicon layers can be formed through LPCVD.
Therefore, the claimed invention would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art because a person of ordinary skill has good reason to pursue the known options within his or her technical grasp, in the instant case choosing the method of forming the polysilicon layers to be LPCVD; if this leads to the anticipated success, in the instant case a material that conducts electricity, it is likely the product not of innovation but of ordinary skill.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOSEPH C NICELY whose telephone number is (571)270-3834. The examiner can normally be reached Monday-Friday 7:30 am - 4 pm, EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JOSEPH C. NICELY
Primary Examiner
Art Unit 2813
/JOSEPH C. NICELY/Primary Examiner, Art Unit 2813
12/12/2025