DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Response to Amendment
The amendment filed June 1, 2026 has been entered. Claims 1-4 and 6-8 remain pending in this application. Claims 1 and 8 have been amended. No claims have been added. No new matter has been added.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3, and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,025,390 B2 to Jun Nakai, et al. (hereafter Nakai) in view of US 9,021,158 B2 to Jea Woong Hyun, et al. (hereafter Hyun) and further in view of US 6,930,925 B2 to Jason Xiaojiang Guo, et al. (hereafter Guo).
Regarding Amended Independent Claim 1, Nakai discloses a semiconductor device comprising:
an electrically writable or erasable non-volatile memory (Disclosing a nonvolatile semiconductor memory device: Nakai, col.2:10-11)
that executes a write operation and an erase operation by respectively applying a write voltage (Applying a write voltage to memory cells: Nakai, col.2:49-51) and an erase voltage on a selection line in the non-volatile memory (Applying an erase voltage to memory cells: Nakai, col.3.51-53); and
a control circuit configured to:
control a rewrite operation including a write operation and an erase operation of the non-volatile memory (Control unit 7 capable of controlling the operations of the memory: Nakai, col.3:6-9);
output, to the non-volatile memory, a rewrite suspension request signal for suspending the rewrite operation of the non-volatile memory (Disclosing a reset command to interrupt an erase operation: Nakai, col.4:3-6); and
output, to the non-volatile memory, a rewrite recovery request signal for recovering from the suspension of the rewrite operation of the non-volatile memory (Disclosing a signal to restart the erase operation following an interruption: Nakai, col.4:36-38),
wherein the non-volatile memory includes:
a rewrite control circuit configured to:
(a) suspend the application of the write voltage or the erase voltage in response to receiving the rewrite suspension request signal (Suspending the erase operation upon receiving the reset command: Nakai, col.4:17-18; The disjunctive ‘or’ in the claim covers suspending either A. the write voltage, B. the erase voltage, or C. both. In disclosing a suspension of the erase voltage in response to a signal, Nakai anticipates the genus through the disclosure of the species. See MPEP § 2131.02(III) and In re Slayter, 125 USPQ 345,276 F.2d 408);
(b) recover from the suspension of the application of the write voltage or the erase voltage in response to receiving the rewrite recovery request signal (Recovering from the suspension of the operation upon receiving a resume instruction: Nakai, col.4:35-38); and
(c) activate a voltage application stop flag and (Setting a ready/busy control flag in the controller: Nakai, col.4:9-13) output, to the control circuit, the voltage application stop flag when the application of the write voltage or the erase voltage is stopped in response to the rewrite suspension request signal (Outputting data to a register in response to receiving the reset command: Nakai, col.4:18-20), the activated voltage application stop flag signaling to the control circuit that the application of the write voltage or the erase voltage has been stopped and that the control circuit may issue the rewrite recovery request signal (The ready/busy flag being set after the erase sequence has ended: Nakai, col.4:9-10); and
wherein the control circuit
receives a suspension instruction when the non-volatile memory is in a write mode or an erase mode (Control circuit 7 receiving a reset signal during an operation: Nakai, col.4:17-18),
transmits the rewrite suspension request signal to the rewrite control circuit based on the received suspension instruction (Interrupting the operation upon receipt of the reset command: Nakai, col.4:17-18), and
outputs the rewrite recovery request signal to the rewrite control circuit when the voltage application stop flag outputted from the rewrite control circuit is active (Control circuit 7 outputting a status signal to Selection circuit 43: Nakai, Figure 10).
Nakai discloses immediately suspending the current write or erase operation in response to the suspension instruction and does not teach completing the current program/erase operation cycle prior to the suspension. Hyun, however, discloses a program/erase suspension methodology, wherein:
wherein,
i) when the rewrite suspension request signal (In response to a suspension request: Hyun, col.11:24-27) is received during application of the write voltage or the erase voltage to the first selection line (During a write operation: Hyun, col.10:65-66),
the rewrite control circuit continues the application of the write voltage or the erase voltage to the first selection line until completion of a predetermined application time for the first selection line (The control circuit optionally completes the current phase of programming: Hyun, col.9:17-21), and
in both cases, stops the application only
after the completion of the predetermined application time and before starting application of the write voltage or the erase voltage to the second selection line selected after the first selection line (If the write/erase cycle continues the current phase until the completion of the current cycle, then it will inherently only stop the current cycle after the completion of that cycle.), and
wherein, after the suspension (Resuming the programming operation after the end of the interrupting operation: Hyun, col.11:53-54),
the rewrite control circuit starts application of the write voltage or the erase voltage to the second selection line (Resuming the original write operation following the end of the interrupting operation at the same point at which it left off: Hyun, col.11:58-62)
in response to receiving the rewrite recovery request signal (In response to a resume command from the controller: Hyun, col.11:55-58).
Hyun teaches allowing a long programming operation to be interrupted prevents memory access requests from becoming queued behind a program operation (Hyun, col.4:1-5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the programming operation interrupt system of Hyun with the interrupt signaling method of Nakai, with a reasonable expectation of success. Both inventions are well known in the field of write/erase operation interrupt efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Nakai and Hyun both disclose processes in which the write/erase operation is suspended in order to perform the interrupting operation and then resumes from the same location following the completion of the interrupting read. Therefore, these disclosures do not teach a rewrite information holding circuit that holds identification information for identifying a second selection line to be selected next, after a first selection line to which the write voltage or the erase voltage was being applied at a time of responding to the rewrite suspension request signal, the rewrite control circuit selecting the first selection line and applies the write voltage or the erase voltage to the first selection line for the predetermined application time when the rewrite suspension request signal is received before application of the write voltage or the erase voltage to the first selection line, or applying the write voltage or the erase voltage to the second selection line without re-applying the write voltage or the erase voltage to the first selection line.
Guo, however, discloses a semiconductor memory device wherein the write/erase operations are milestoned by a series of breakpoints, logically aligned with source lines. Once an operation begins, it continues to the next breakpoint even if an interruption occurs. Therefore, it discloses a device including:
a rewrite information holding circuit that holds
identification information for identifying a second selection line to be selected next (Setting the next break point following an interruption: Guo, col.4:3-5), after a first selection line to which the write voltage or the erase voltage was being applied at a time of responding to the rewrite suspension request signal (Following an interruption: Guo, col.3:53-64),
wherein,
when the rewrite suspension request signal is received before application of the write voltage or the erase voltage to the first selection line, the rewrite control circuit selects the first selection line and applies the write voltage or the erase voltage to the first selection line for the predetermined application time (When the interruption occurs during pre-charge, before application of the write/erase pulse, the control circuit continues to complete the operation through the first breakpoint: Guo, col.2:47-55), and
applies the write voltage or the erase voltage to the second selection line without re-applying the write voltage or the erase voltage to the first selection line (Restarting the operation at the point following the first break point and proceeding on to at least the next break point: Guo, col.2:60-3:5).
Guo teaches this method allows for a full programming operation to take place consistently, with the same duration with or without suspend and with more uniform cell margins (Guo, col.2:43-46). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the breakpoint programming method of Guo with the stable interruption system of Hyun and the interrupt signaling method of Nakai, with a reasonable expectation of success. All three inventions are well known in the field of semi-conductor write/erase interrupt operations and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 3, Nakai discloses the semiconductor device according to claim 1,
wherein, when the rewrite control circuit receives the rewrite suspension request signal before the application of the write voltage or the erase voltage to a first selection line to be selected in a write mode or an erase mode,
the rewrite control circuit selects the first selection line and completes the application of the write voltage or the erase voltage to the first selection line (Disclosing starting the erase operation from the beginning on early interruption: Nakai, col.7:65-8:5) and, thereafter,
the rewrite information holding circuit receives, from the rewrite recovery control circuit, identification information of a selection line to be selected next after the first selection line (Disclosing storing the current state of the erase operation in a register: Nakai, col.8:60-62),
wherein, when the rewrite control circuit receives the rewrite suspension request signal during an application of a write voltage or erase voltage to a second selection different from the last selection line to be selected in the write mode or the erase mode,
the rewrite control circuit completes the application of the write voltage or erase voltage to the second selection line (Disclosing completing the erase operation following an interruption from the prior position of the operation: Nakai, col.6:21-27) and, thereafter,
the rewrite information holding circuit receives, from the rewrite control circuit, identification information of a selection line to be selected next after the second selection line (Disclosing storing the current state of the erase operation in a register: Nakai, col.8:60-62), and
wherein when the rewrite control circuit receives the rewrite suspension request signal from the control circuit, the rewrite control circuit:
reads the identification information of a next selection line to be selected next from the rewrite information holding circuit (Disclosing storing the current state of the erase operation in a register: Nakai, 8:60-62);
selects the next selection line to be selected next indicated in the identification information (Identifying the next line for the erase operation: Nakai, col.4:51-54); and
applies the write voltage or the erase voltage to the selected next selection line (Applying the next step erase voltage to the selected erase line: Nakai, col.4:64-67).
Regarding Amended Independent Claim 8, Nakai discloses a semiconductor device having
an electrically writable or erasable non- volatile memory (Disclosing a nonvolatile semiconductor memory device: Nakai, col.2:10-11) and
a control circuit for controlling a rewrite operation including at least one of
a write operation and an erase operation of the non-volatile memory
by respectively applying a write voltage and an erase voltage on a selection line in the non-volatile memory (Disclosing a control unit for the memory cell array: Nakai, col.2:11-12),
wherein the non-volatile memory includes:
a rewrite control circuit receives, from the control circuit, a rewrite suspension request signal for suspending the rewrite operation by suspending the application of the write voltage or the erase voltage (Disclosing a register that responds to the suspension instruction during an erase operation: Nakai, Figure 4; See Also, Nakai, col.4:3-7),
receives, from the control circuit, a rewrite recovery request signal for recovering from the suspension of the rewrite operation (Disclosing a register that responds to the suspension instruction during an erase operation: Nakai, Figure 4; See Also, Nakai, col.4:3-7),
performs a recovery operation to recover from the suspension of the application of the write voltage or the erase voltage (Controlling the recovery operation from the suspension of the application: Nakai, 4:3-16), and
activates and outputs a voltage application stop flag to the control circuit in response to suspending the application of the write voltage or the erase voltage (Disclosing a reset command to the control unit to interrupt an erase operation: Nakai, 4:3-6),
the activated voltage application stop flag signaling to the control circuit that the application of the write voltage or the erase voltage has been stopped and that the control circuit may issue the rewrite recovery request signal (The ready/busy flag being set after the erase sequence has ended: Nakai, col.4:9-10).
Nakai discloses immediately suspending the current write or erase operation in response to the suspension instruction and does not teach completing the current program/erase operation cycle prior to the suspension. Hyun, however, discloses a program/erase suspension methodology, wherein:
i) when the rewrite suspension request signal (In response to a suspension request: Hyun, col.11:24-27) is received during application of the write voltage or the erase voltage is being applied to a first selection line (During a write operation: Hyun, col.10:65-66),
the rewrite control circuit continues the application of the write voltage or the erase voltage to the first selection line until completion of a predetermined application time for the first selection line (The control circuit optionally completes the current phase of programming: Hyun, col.9:17-21),
in both cases, stops the application only
after the completion of the predetermined application time and before starting application of the write voltage or the erase voltage to a second selection line selected after the first selection line (If the write/erase cycle continues the current phase until the completion of the current cycle, then it will inherently only stop the current cycle after the completion of that cycle.), and
wherein, after the suspension (Resuming the original write operation following the end of the interrupting operation at the same point at which it left off: Hyun, col.11:58-62) and in response to receiving the rewrite recovery request signal (In response to a resume command from the controller: Hyun, col.11:55-58).
Hyun teaches allowing a long programming operation to be interrupted prevents memory access requests from becoming queued behind a program operation (Hyun, col.4:1-5). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the programming operation interrupt system of Hyun with the interrupt signaling method of Nakai, with a reasonable expectation of success. Both inventions are well known in the field of write/erase operation interrupt efficiency and the combination of known inventions with predictable results is obvious and not patentable.
Guo, however, discloses a semiconductor memory device wherein the write/erase operations are milestoned by a series of breakpoints, logically aligned with source lines. Once an operation begins, it continues to the next breakpoint even if an interruption occurs. Therefore, it discloses a device wherein:
when the rewrite suspension request signal is received before application of the write voltage or the erase voltage to the first selection line, the rewrite control circuit selects the first selection line and applies the write voltage or the erase voltage to the first selection line for the predetermined application time (When the interruption occurs during pre-charge, before application of the write/erase pulse, the control circuit continues to complete the operation through the first breakpoint: Guo, col.2:47-55), and
the rewrite control circuit controls a write operation or an erase operation to another region different from a region in which the write operation or erase operation is stopped without re-applying the write voltage or the erase voltage to the first selection line (Restarting the operation at the point following the first break point and proceeding on to at least the next break point: Guo, col.2:60-3:5).
Guo teaches this method allows for a full programming operation to take place consistently, with the same duration with or without suspend and with more uniform cell margins (Guo, col.2:43-46). Therefore, it would have been obvious to one having ordinary skill in the art, before the effective filing date of this application, to combine the breakpoint programming method of Guo with the stable interruption system of Hyun and the interrupt signaling method of Nakai, with a reasonable expectation of success. All three inventions are well known in the field of semi-conductor write/erase interrupt operations and the combination of known inventions with predictable results is obvious and not patentable.
Claim(s) 2, 4, and 6-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 9,025,390 B2 to Jun Nakai, et al. (hereafter Nakai), US 9,021,158 B2 to Jea Woong Hyun, et al. (hereafter Hyun), and US 6,930,925 B2 to Jason Xiaojiang Guo, et al. (hereafter Guo) in view of US 11,282,576 B2 Cho Rong Park, et al. (hereafter Park).
Regarding Claim 2, Nakai discloses the semiconductor device according to claim 1 and suggests some of the further limitations of Claim 2, some of which may be inherent in the operation of Nakai. Park, however, expressly discloses a device as in Claim 1, wherein the rewrite control circuit is configured to:
in receiving the rewrite suspension request signal before an application of a write voltage or erase voltage to a first selection line to be selected in the write mode or the erase mode,
select the first selection line,
interrupt the write mode or the erase mode after the application of the write voltage or the erase voltage to the first selection line (Interrupting an erase operation in response to a suspend command: Park, col.5:55-61), and
activate the voltage application stop flag and
output the activated voltage application stop flag to the control circuit (Disclosing a timing condition to when a suspension instruction interrupted the erase operation, starting at first offset 1: Park, col.19:26-30);
in receiving the rewrite suspension request signal during the application of the write voltage or the erase voltage to a second selection line different from a last selection line to be selected in the write mode or the erase mode,
interrupt the write mode or the erase mode after completion of the application of the write voltage or the erase voltage to the second selection line (Interrupting an erase operation in response to a suspend command: Park, col.5:55-61), and
activate the voltage application stop flag and
output the activated voltage application stop flag to the control circuit (Disclosing interrupting an erase operation for the duration of a higher priority operation: Park col.20:10-14);
in receiving the rewrite suspension request signal during the application of the write voltage or the erase voltage to the last selection line to be selected in the write mode or the erase mode,
interrupt the write mode or the erase mode after completing the application of the write voltage or the erase voltage to the last selection line (Interrupting an erase operation in response to a suspend command: Park, col.5:55-61), and
deactivate the voltage application stop flag and
output the deactivated voltage application stop flag to the control circuit (Disclosing continuing the erase operation following an interruption unless the erase operation had previously reached specific threshold: Park, col.20:31-34); and
in receiving the rewrite suspension request signal after the application of the write voltage or the erase voltage to the last selection line to be selected in the write mode or the erase mode,
deactivate the voltage application stop flag to output it and
output the deactivated voltage application stop flag to the control circuit (Concluding the erase operation once the erase operation has reached an effective conclusion: Park col.20:48-52).
The timing behavior described above is inherent in Nakai based on the logic of the circuits. This behavior is not explicit, however. It is made explicit in Park, which tracks this data specifically to avoid over-erasure, identified as a concern in Nakai (Teaching that over-erasure can result in degradation of memory cells: Nakai 4:31-34). Park further teaches this interruption technique permits higher priority operations to assume control of a memory device during a lengthy erase operation (Park, col.5:58-65).
Therefore, it would have been obvious, before the effective filing date of this application, to combine the the interruption controls of Park with the reset system of Nakai, with a reasonable expectation of success. Both inventions are well known in the field of low-priority operation interruption and resume in memory systems, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 4, Nakai discloses the semiconductor device according to claim 1, but doesn’t expressly disclose the further limitations of Claim 4. Park, however, discloses a device as in Claim 1, wherein
wherein the rewrite information holding circuit stores write time information from when the write voltage is applied to the selection line to when the application of the write voltage is suspended in addition to the write position information, or wherein the rewrite information holding circuit stores erase time information from when the erase voltage is applied to the selection line to when the application of the erase voltage is suspended in addition to the erase position information (Disclosing storing the erase operation time information: Park, col.18:45-47), and
wherein, when the rewrite control circuit receives the recovery request signal,
the rewrite control circuit reads the write position information the write time information or the erase position information and erase time information from the rewrite information holding circuit (Disclosing generating and using erase voltage and time offset following an interruption: Park, 18:60-67),
selects a selection line indicated by the write position information or the erase position information, and applies the write voltage or the erase voltage to the selected selection line for a remaining time to be applied to the selection line based on the write time information or the erase time information (Disclosing subsequently applying an erase voltage determined by the erase information: Park, 19:1-4).
Park teaches this interruption technique permits higher priority operations to assume control of a memory device during a lengthy erase operation (Park, col.5:58-65).
Therefore, it would have been obvious, before the effective filing date of this application, to combine the the interruption controls of Park with the reset system of Nakai, with a reasonable expectation of success. Both inventions are well known in the field of low-priority operation interruption and resume in memory systems, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 6, Nakai discloses the semiconductor device according to claim 1, but does not explicitly disclose the further limitations of Claim 6. Park, however, discloses a semiconductor device as in Claim 1, wherein:
the selection line is a source line of the non-volatile memory (Disclosing source lines SSL1 and SSL2 as selection lines: Park, Figure 4),
wherein the source line is composed of a plurality of source lines (Disclosing multiple source lines SSL1 and SSL2: Park, Figure 4), and
wherein each of the plurality of source lines corresponds to a different storage region of the non-volatile memory (Disclosing source lines SSL1 and SSL2 connected to separate storage regions: Park, Figure 4).
Park teaches this interruption technique permits higher priority operations to assume control of a memory device during a lengthy erase operation (Park, col.5:58-65).
Therefore, it would have been obvious, before the effective filing date of this application, to combine the the interruption controls of Park with the reset system of Nakai, with a reasonable expectation of success. Both inventions are well known in the field of low-priority operation interruption and resume in memory systems, and the combination of known inventions with predictable results is obvious and not patentable.
Regarding Claim 7, Park discloses the semiconductor device according to claim 6, wherein
the selection line further includes a bit line of the non-volatile memory (Disclosing bit lines BL1 through BLm: Park, Figure 4).
Response to Arguments
Applicant’s arguments filed with respect to the claims have been fully considered but are thought to be fully addressed by the modified and new grounds of rejections above. Applicant’s response is considered to be a bona fide attempt at a response and is being accepted as a complete response.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 7,068,566 B2 to Eitaro Otsuka, et al.: Teaching managing multiple read requests to different sections of the memory simultaneously.
US 2013/0124792 A1 to Ashot Melik-Martirosian, et al.: Describing an erase operation with a suspend command that halts the erase following the end of the current step, resuming from the same step upon termination of suspending operation.
US 8,149,622 B2 to Peter Wung Lee, et al.: Teaching write/erase operations capable of being interrupted by a read operation.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/DOUGLAS KING/Primary Examiner, Art Unit 2824
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