DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
1. A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/8/2025 has been entered.
Status of the Application
2. Acknowledgement is made of the amendment received on 9/8/2025. Claims 2-21 are pending in this application. Claim 1 is canceled.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, “the insulating layer is disposed within the substrate…and directly contacts to the first surface” (claims 16 & 18) must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
4. Claims 16 and 18 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, claims 16 & 18 each cites “the insulating layer is disposed within the substrate, between the first surface and the protective layer, and directly contact the first surface” is not clear because of “directly contact the first surface”. Fig. 2 shows insulating layer 20 within substrate 10, and spaced apart from first surface (upper surface of 10). Claim 2 requires “the first surface of the substrate covers an entirely of the insulating layer” & “between the first surface of the substrate and the protective layer”. Reading into claim 2, it is not clear any particular position of the insulating layer within the substrate and how the insulating layer directly contacts the first surface of the substrate.
For best understanding and examination purpose, the claim(s) will be best considered based on drawings, disclosure, and/or any applicable prior arts.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
5. Claims 2-4, 9, 14-18 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Endo (US 6,130,458).
Re claims 2 & 9, Endo teaches, under BRI, Figs. 6B & 12B, cols. 6-7, an integrated circuit device comprising:
-a protected circuit (transistors 5, 6) disposed on a substrate (11, 13), the substrate (11, 13) having a first surface (indicated) and a second surface (indicated) opposite the first surface;
-a protective layer (n layer 39) disposed within the substrate (11, 13), and configured to protect the protected circuit (5, 6) by absorbing laser radiation targeted at the protected circuit (9) through the substrate (11, 13) (for the intended use and characteristic of 39), wherein the protective layer (39) comprises a doped semiconductor (N-type); and
-an insulating layer (oxide film 10) disposed within the substrate (11, 13) such that the first surface of the substrate (11, 13) covers an entirety of the insulating layer (10), the insulating layer (10) being between the first surface of the substrate (11, 13) and the protective layer (39) disposed within the substrate (11, 13), the first surface of the substrate (11, 13) being between the insulating layer (10) and the protected circuit (5, 6) (e.g., between gate G, S/D terminals & 10), a plane of the insulating layer (10) being parallel to a plane of the protective layer (39), and configured to electrically insulate (e.g., as characteristic of insulator) the protected circuit (5, 6) from the protective layer (39) and a portion of the substrate (11, 13) that is on a side of the protective layer (39) that is opposite the insulating layer (10) (e.g., in vertical direction).
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Re claim 3, Endo teaches, Fig. 6B, the protective layer (39) is disposed (within substrate) such that removal of the protective layer (39) causes physical damage (e.g., due to its position within substrate & under circuit 5, 6) to the protective circuit (5, 6).
Re claim 4, Endo teaches, Fig. 6B, intermediate circuitry (in transistor/region 4) protruding into the substrate (11, 13) between the protective layer (39) and the insulating layer (10) (e.g., in horizontal direction) and terminating before contacting the protective layer (39), wherein the physical damage to the protected circuit (5, 6) is physical damage to the intermediate circuitry (in transistor/region 4).
Re claim 14, Endo teaches, Fig. 6B, the protected circuit (5, 6) is disposed on the first surface of the substrate (11, 13) and directly contacts the first surface of the substrate (11, 13).
Re claim 15, Endo teaches, Fig. 6B, the protective layer (39) is disposed within the substrate (11, 13), between the first surface and the second surface (in vertical direction).
Re claim 16, Endo teaches, under BRI, Fig. 6B, the insulating layer (10) is disposed within the substrate (11, 13), between the first surface (indicated) and the protective layer (39), and directly contacts the first surface (indicated) (via 12, in vertical direction).
Re claim 17, Endo teaches, Fig. 6B, the insulating layer (10) disposed within the substrate (11, 13), between the first surface and the protective layer (39) in a cross sectional view.
Re claim 18, Endo teaches, under BRI, Fig. 6B, the protected circuit (5, 6) is disposed on the first surface of the substrate (11, 13), the protective layer (39) is disposed within the substrate (11), between the first surface and the second surface, and the insulating layer (10) is disposed within the substrate (11), between the first surface and the protective layer (39), and directly contacts the first surface (via 12, in vertical direction).
Re claim 21, Endo teaches, under BRI, Figs. 6B & 12B, cols. 6-7, an integrated circuit device comprising:
-a protected circuit (transistors 5, 6) disposed on a substrate (11, 13), the substrate (11, 13) having a first surface and a second surface opposite the first surface (indicated);
-a protective layer (n layer 39) disposed within the substrate (11), and configured to protect the protected circuit (5, 6) by absorbing laser radiation targeted at the protected circuit (9) through the substrate (11) (for the intended use and characteristic of 39), and
-intermediate circuitry (in transistor/region 4) protruding into the substrate (11, 13) between the protected circuit (5, 6) and an insulating layer (10) (in horizontal direction), the integrated circuit device being configured such that removal of the protective layer (39) from the substrate (11, 13) causes physical damage (e.g., due to its position under 5, 6) that disables the protected circuit (5, 6),
-wherein the insulating layer (oxide film 10) disposed within the substrate (11, 13) such that the first surface of the substrate (11, 13) covers an entirety of the insulating layer (10), the insulating layer (10) being between the first surface of the substrate (11, 13) and the protective layer (39) disposed within the substrate (11, 13), the first surface of the substrate (11, 13) being between the insulating layer (10) and the protected circuit (5, 6) (e.g., between gate G, S/D terminals & 10), a plane of the insulating layer (10) being parallel to a plane of the protective layer (39), and configured to electrically insulate (e.g., as characteristic of insulator) the protected circuit (5, 6) from the protective layer (39) and a portion of the substrate (11, 13) that is on a side of the protective layer (39) that is opposite the insulating layer (10) (e.g., in vertical direction, and
wherein the physical damage (e.g., due to position of 39 under 5, 6 & circuit in transistor/region 4) that disables the protected circuit (5, 6) is a physical damage to the intermediate circuitry.
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Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
6. Claims 5-8, 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Endo.
The teachings of Endo have been discussed above.
Re claim 5, Endo teaches under BRI, Fig. 6B, col. 7, 1st par., detection circuitry (e.g., protection circuits/current detection circuits) configured to detect (for the intended use) a change in an electrical property of the integrated circuit device indicative of removal of the protective layer (39), and, in response to detecting the change in the electrical property, cause the protected circuit (5, 6) to be disabled.
Endo does not explicitly teach the detection circuit disposed in a same layer of the integrated circuit as the protected circuit.
Endo does teach, col. 7, 1st par. “it is of course possible to integrate also protection circuits, current detection circuits, and small-signal circuits on the same semiconductor chip”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Endo to obtain the detection circuit disposed in a same layer of the integrated circuit as the protected circuit as claimed to achieve a desired structure of the formed circuit device. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Re claim 6, Endo teaches the electrical property is capacitance (based on capacitors & decreasing of capacitance) (abstract & claim 1).
Re claim 7, Endo teaches the detection circuitry comprises a DRAM cell or a bipolar transistor (claim 10).
Re claim 8, Endo teaches, Fig. 6B, intermediate detection circuitry (in transistor/region 4) protruding into the substate (11, 13) between the protective layer (39) and the protected circuit (5, 6) (in horizontal direction).
Re claim 19, Endo’s Fig. 6B does not explicitly teach the protective layer is continuous over an entirety of the substrate.
Endo’s Fig. 11 teaches the protective layer (39) is continuous over an entirety of the substrate (11).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Endo to obtain the protective layer is continuous over an entirety of the substrate as claimed, because it aids in achieving a desired structure & resistivity of protective layer & aids in compensating a relatively large potential difference in a floating state.
Re claim 20, Endo teaches, under BRI, Figs. 6B & 12B, cols. 6-7, an integrated circuit device comprising:
-a protected circuit (transistors 5, 6) disposed on a substrate (11, 13), the substrate (11, 13) having a first surface and a second surface opposite the first surface (indicated);
-a protective layer (n layer 39) disposed within the substrate (11, 13), and configured to protect the protected circuit (5, 6) by absorbing laser radiation targeted at the protected circuit (9) through the substrate (11) (for the intended use and characteristic of 39),
-detection circuitry (e.g., protection circuits/current detection circuits) configured to detect (as intended use or as function of detection circuits) a change in an electrical property of the integrated circuit device indicative of removal of the protective layer (39) from the substrate (11), and, in response to detecting the change in the electrically property, cause the protected circuit (5, 6) to be disabled; and
-an insulating layer (oxide film 10) disposed within the substrate (11, 13) such that the first surface of the substrate (11, 13) covers an entirely of the insulating layer (10), the insulating layer (10) being between the first surface of the substrate (11, 13) and the protective layer (39) disposed within the substrate (11, 13), the first surface of the substrate being between the insulating layer (10) and the protected circuit (5, 6) (e.g., between gate G, S/D terminals & 10), a plane of the insulating layer (10) being parallel to a plane of the protective layer (39), between the protective layer (39) and protected circuit (5, 6), and configured to electrically insulate (e.g., as characteristic of insulator) the protected circuit (5, 6) from the protective layer (39) and a portion of the substrate (11, 13) that is on a side of the protective layer (39) that is opposite the insulating layer (10) (e.g., in vertical direction).
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Endo does not explicitly teach the detection circuit disposed in a same layer of the integrated circuit as the protected circuit.
Endo does teach, col. 7, 1st par. “it is of course possible to integrate also protection circuits, current detection circuits, and small-signal circuits on the same semiconductor chip”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Endo to obtain the detection circuit disposed in a same layer of the integrated circuit as the protected circuit as claimed to achieve a desired structure of the formed circuit device. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
7. Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Endo in view of Cade (US 4,534,804).
The teachings of Endo have been discussed above.
Re claims 10 & 11, Endo does not explicitly teach the doped semiconductor has a dopant concentration of 1019 cm-3, 1020 cm-3, 5x1020 cm-3 or 1021 cm-3 and the protective layer has the transmittance of the laser radiation that is less than or equal to one of 40 %, 20 %, 15 %, 10 %, 5 %, or 2 %.
Cade teaches “The dividing line between "heavily" doped and "lightly" doped is 3x1018 atoms of dopant per cubic centimeter” (col. 3, lines 50-51).
As taught by Cade, one of ordinary skill in the art would utilize/modify the above teaching to obtain the doped semiconductor has a dopant concentration of 1019 cm-3, 1020 cm-3, 5x1020 cm-3 or 1021 cm-3 & to obtain the transmittance of the laser radiation that is less than or equal to one of 40 %, 20 %, 15 %, 10 %, 5 %, or 2 % as claimed, because dopant concentration/transmittance of laser radiation of a semiconductor layer depended on many variable parameters such as thickness, material, desired device requirement, dopant, surrounding layers, temperature, pressure, etc., and are known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited concentration/transmittance through routine experimentation to achieve desired characteristics of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cade in combination Endo due to above reason.
Re claim 12, in combination cited above, Cade teaches the laser radiation is infra-red radiation (col. 3, 2nd par.).
Re claim 13, in combination cited above, Cade teaches the protective layer has a transmittance of laser radiation that is less than a transmittance of laser radiation in the substrate (abstract, col. 1, lines 45-52 & last par.).
Double Patenting
8. The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 2-21 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-14 of U.S. Patent No.11,658,133 and/or in view of Endo (US 6,130,458). Although the claims at issue are not identical, they are not patentably distinct from each other because they both claim and require similar features including protective circuit on substrate, protective layer within the substrate, insulating layer within the substrate, intermediate circuitry, and detection circuitry, etc; and Endo teaches the first surface of the substrate covers an entirety of the insulating layer.
18/299,419
2. An integrated circuit device comprising:
a protected circuit disposed on a substrate, the substrate having a first surface and a second surface opposite the first surface;
a protective layer disposed within the substrate, and configured to protect the protected circuit by absorbing laser radiation targeted at the protected circuit through the substrate; and
an insulating layer disposed within the substrate such that the first surface of the substrate covers an entirely of the insulating layer, the insulating layer being between the first surface of the substrate and the protective layer disposed within the substrate, the first surface of the substrate being between the insulating layer and the protected circuit, a plane of the insulating layer being parallel to a plane of the protective layer, and configured to electrically insulate the protected circuit from the protective layer and a portion of the substrate that is on a side of the protective layer that is opposite the insulating layer.
17. The integrated circuit device as claimed in claim 2, wherein the substrate has a first surface and a second surface opposite the first surface, and
the insulating layer is disposed within the substrate, between the first surface and the protective layer in a cross sectional view.
19. The integrated circuit device as claimed in claim 2, wherein the protective layer is continuous over an entirety of the substrate.
11,658,133
1. An integrated circuit device comprising: a substrate having a first surface and a second surface opposite the first surface; a protected circuit disposed on the first surface of the substrate; a protective layer disposed within the substrate, between the first surface and the second surface, and configured to protect the protected circuit by absorbing laser radiation targeted at the protected circuit through the substrate, the protective layer being continuous over an entirety of the substrate; and an insulating layer disposed within the substrate, between the first surface and the protective layer in a cross sectional view, and configured to electrically insulate the protected circuit from the protective layer and a portion of the substrate that is on a side of the protective layer that is opposite the insulating layer.
Response to Arguments
9. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
The claims are amended with newly added features, interpretation & rejection under Endo also changed to meet the current claims. Details included in the above rejection.
Conclusion
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, EVA MONTALVO can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 1/21/26