DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
1. Acknowledgement is made of the amendment received on 4/1/2026. Claims 2-21 are pending in this application. Claim 1 is canceled.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 2-9 and 14-21 are rejected under 35 U.S.C. 103 as being unpatentable over Endo (US 6,130,458) in view of Stuber et al. (US 2015/0137307).
Re claims 2 & 9, Endo teaches, under BRI, Figs. 6B & 12B, cols. 6-7, an integrated circuit device comprising:
-a protected circuit (transistors 5, 6) disposed on a substrate (11, 13), the substrate (11, 13) having a first layer (13) and a second layer (11) opposite the first layer (13);
-a protective layer (n layer 39) disposed within the substrate (11, 13), and configured to protect the protected circuit (5, 6) by absorbing laser radiation targeted at the protected circuit (9) through the substrate (11, 13) (for the intended use and characteristic of 39), wherein the protective layer (39) comprises a doped semiconductor (N-type); and
-an insulating layer (oxide film 10) disposed within the substrate (11, 13) such that the first layer (13) of the substrate (11, 13) covers an entirety of the insulating layer (10), the insulating layer (10) being between the first layer of the substrate (11, 13) and the protective layer (39) disposed within the substrate (11, 13), the first layer (13) of the substrate (11, 13) being between the insulating layer (10) and the protected circuit (5, 6) (e.g., between gate G, S/D terminals & 10), the protected circuit (5, 6) being disposed on the first layer (13) of the substrate (11, 13), a plane of the insulating layer (10) being parallel to a plane of the protective layer (39), and configured to electrically insulate (e.g., as characteristic of insulator) the protected circuit (5, 6) from the protective layer (39) and a portion of the substrate (11, 13) that is on a side of the protective layer (39) that is opposite the insulating layer (10) (e.g., in vertical direction).
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Endo does not explicitly teach an entirely of the protected circuit being disposed on the first layer of the substrate.
Stuber teaches, Fig. 4B, [0033, 0034], an entirely of the protected circuit (240) being disposed on the first layer (220) of the substrate (210, 220).
As taught by Stuber, one of ordinary skill in the art would utilize & modify the above teaching into Endo to obtain an entirely of the protected circuit being disposed on the first layer of the substrate as claimed, because it aids in achieving the maximum flexibility in circuit layout & minimizing the size of an integrated circuit. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Stuber in combination Endo due to above reason.
Re claim 3, Endo teaches, Fig. 6B, the protective layer (39) is disposed (within substrate) such that removal of the protective layer (39) causes physical damage (e.g., due to its position within substrate & under circuit 5, 6) to the protective circuit (5, 6).
Re claim 4, Endo teaches, Fig. 6B, intermediate circuitry (in transistor/region 4) protruding into the substrate (11, 13) between the protective layer (39) and the insulating layer (10) (e.g., in horizontal direction) and terminating before contacting the protective layer (39), wherein the physical damage to the protected circuit (5, 6) is physical damage to the intermediate circuitry (in transistor/region 4).
Re claim 5, Endo teaches under BRI, Fig. 6B, col. 7, 1st par., detection circuitry (e.g., protection circuits/current detection circuits) configured to detect (for the intended use) a change in an electrical property of the integrated circuit device indicative of removal of the protective layer (39), and, in response to detecting the change in the electrical property, cause the protected circuit (5, 6) to be disabled.
Endo/Stuber does not explicitly teach the detection circuit disposed in a same layer of the integrated circuit device as the protected circuit.
Endo does teach, col. 7, 1st par. “it is of course possible to integrate also protection circuits, current detection circuits, and small-signal circuits on the same semiconductor chip”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Endo to obtain the detection circuit disposed in a same layer of the integrated circuit as the protected circuit as claimed to achieve a desired structure of the formed circuit device. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Re claim 6, Endo teaches the electrical property is capacitance (based on capacitors & decreasing of capacitance) (abstract & claim 1).
Re claim 7, Endo teaches the detection circuitry comprises a DRAM cell or a bipolar transistor (claim 10).
Re claim 8, Endo teaches, Fig. 6B, intermediate detection circuitry (in transistor/region 4) protruding into the substate (11, 13) between the protective layer (39) and the protected circuit (5, 6) (in horizontal direction).
Re claim 14, Endo teaches, Fig. 6B, the protected circuit (5, 6) is disposed on the first layer (13) of the substrate (11, 13) and directly contacts the first layer (13) of the substrate (11, 13).
Re claim 15, Endo teaches, Fig. 6B, the protective layer (39) is disposed within the substrate (11, 13), between the first layer (13) and the second layer (11) (in vertical direction).
Re claim 16, Endo teaches, under BRI, Fig. 6B, the insulating layer (10) is disposed within the substrate (11, 13), between the first layer (13) and the protective layer (39), and directly contacts the first layer (13).
Re claim 17, Endo teaches, Fig. 6B, the insulating layer (10) disposed within the substrate (11, 13), between the first layer (13) and the protective layer (39) in a cross sectional view.
Re claim 18, Endo teaches, under BRI, Fig. 6B, the protected circuit (5, 6) is disposed on the first layer (13) of the substrate (11, 13), the protective layer (39) is disposed within the substrate (11, 13), between the first layer (13) and the second layer (11), and the insulating layer (10) is disposed within the substrate (11, 13), between the first layer (13) and the protective layer (39), and directly contacts the first layer (13).
Re claim 19, Endo/Stuber does not explicitly teach the protective layer is continuous over an entirety of the substrate.
Endo’s Fig. 11 teaches the protective layer (39) is continuous over an entirety of the substrate (11).
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ & modify the teaching as taught by Endo to obtain the protective layer is continuous over an entirety of the substrate as claimed, because it aids in achieving a desired structure & resistivity of protective layer & aids in compensating a relatively large potential difference in a floating state.
Re claim 20, Endo teaches, under BRI, Figs. 6B & 12B, cols. 6-7, an integrated circuit device comprising:
-a protected circuit (transistors 5, 6) disposed on a substrate (11, 13), the substrate (11, 13) having a first layer (13) and a second layer (11) opposite the first layer (13);
-a protective layer (n layer 39) disposed within the substrate (11, 13), and configured to protect the protected circuit (5, 6) by absorbing laser radiation targeted at the protected circuit (9) through the substrate (11) (for the intended use and characteristic of 39),
-detection circuitry (e.g., protection circuits/current detection circuits) configured to detect (as intended use or as function of detection circuits) a change in an electrical property of the integrated circuit device indicative of removal of the protective layer (39) from the substrate (11), and, in response to detecting the change in the electrically property, cause the protected circuit (5, 6) to be disabled; and
-an insulating layer (oxide film 10) disposed within the substrate (11, 13) such that the first layer (13) of the substrate (11, 13) covers an entirely of the insulating layer (10), the insulating layer (10) being between the first layer (13) of the substrate (11, 13) and the protective layer (39) disposed within the substrate (11, 13), the first layer (13) of the substrate being between the insulating layer (10) and the protected circuit (5, 6) (e.g., between gate G, S/D terminals & 10), the protected circuit (5, 6) being disposed on the first layer (13) of the substrate (11, 13), a plane of the insulating layer (10) being parallel to a plane of the protective layer (39), between the protective layer (39) and protected circuit (5, 6), and configured to electrically insulate (e.g., as characteristic of insulator) the protected circuit (5, 6) from the protective layer (39) and a portion of the substrate (11, 13) that is on a side of the protective layer (39) that is opposite the insulating layer (10) (e.g., in vertical direction).
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Endo does not explicitly teach the detection circuit disposed in a same layer of the integrated circuit device as the protected circuit.
Endo does teach, col. 7, 1st par. “it is of course possible to integrate also protection circuits, current detection circuits, and small-signal circuits on the same semiconductor chip”.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ/modify the teaching as taught by Endo to obtain the detection circuit disposed in a same layer of the integrated circuit as the protected circuit as claimed to achieve a desired structure of the formed circuit device. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Endo does not explicitly teach an entirely of the protected circuit being disposed on the first layer of the substrate.
Stuber teaches, Fig. 4B, [0033, 0034], an entirely of the protected circuit (240) being disposed on the first layer (220) of the substrate (210, 220).
As taught by Stuber, one of ordinary skill in the art would utilize & modify the above teaching into Endo to obtain an entirely of the protected circuit being disposed on the first layer of the substrate as claimed, because it aids in achieving the maximum flexibility in circuit layout & minimizing the size of an integrated circuit. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Stuber in combination Endo due to above reason.
Re claim 21, Endo teaches, under BRI, Figs. 6B & 12B, cols. 6-7, an integrated circuit device comprising:
-a protected circuit (transistors 5, 6) disposed on a substrate (11, 13), the substrate (11, 13) having a first layer (13) and a second layer (11) opposite the first layer (13);
-a protective layer (n layer 39) disposed within the substrate (11), and configured to protect the protected circuit (5, 6) by absorbing laser radiation targeted at the protected circuit (9) through the substrate (11) (for the intended use and characteristic of 39), and
-intermediate circuitry (in transistor/region 4) protruding into the substrate (11, 13) between the protected circuit (5, 6) and an insulating layer (10) (in horizontal direction), the integrated circuit device being configured such that removal of the protective layer (39) from the substrate (11, 13) causes physical damage (e.g., due to its position under 5, 6) that disables the protected circuit (5, 6),
-wherein the insulating layer (oxide film 10) disposed within the substrate (11, 13) such that the first layer (13) of the substrate (11, 13) covers an entirety of the insulating layer (10), the insulating layer (10) being between the first layer (13) of the substrate (11, 13) and the protective layer (39) disposed within the substrate (11, 13), the first layer (13) of the substrate (11, 13) being between the insulating layer (10) and the protected circuit (5, 6) (e.g., between gate G, S/D terminals & 10), the protected circuit (5, 6) being disposed on the first layer of the substrate (11, 13), a plane of the insulating layer (10) being parallel to a plane of the protective layer (39), and configured to electrically insulate (e.g., as characteristic of insulator) the protected circuit (5, 6) from the protective layer (39) and a portion of the substrate (11, 13) that is on a side of the protective layer (39) that is opposite the insulating layer (10) (e.g., in vertical direction, and
wherein the physical damage (e.g., due to position of 39 under 5, 6 & circuit in transistor/region 4) that disables the protected circuit (5, 6) is a physical damage to the intermediate circuitry.
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Endo does not explicitly teach an entirely of the protected circuit being disposed on the first layer of the substrate.
Stuber teaches, Fig. 4B, [0033, 0034], an entirely of the protected circuit (240) being disposed on the first layer (220) of the substrate (210, 220).
As taught by Stuber, one of ordinary skill in the art would utilize & modify the above teaching into Endo to obtain an entirely of the protected circuit being disposed on the first layer of the substrate as claimed, because it aids in achieving the maximum flexibility in circuit layout & minimizing the size of an integrated circuit. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Stuber in combination Endo due to above reason.
3. Claims 10-13 are rejected under 35 U.S.C. 103 as being unpatentable over Endo as modified by Stuber as applied to claims 2 & 9 above, in view of Cade (US 4,534,804).
The teachings of Endo/Stuber have been discussed above.
Re claims 10 & 11, Endo/Stuber does not explicitly teach the doped semiconductor has a dopant concentration of 1019 cm-3, 1020 cm-3, 5x1020 cm-3 or 1021 cm-3 and the protective layer has the transmittance of the laser radiation that is less than or equal to one of 40 %, 20 %, 15 %, 10 %, 5 %, or 2 %.
Cade teaches “The dividing line between "heavily" doped and "lightly" doped is 3x1018 atoms of dopant per cubic centimeter” (col. 3, lines 50-51).
As taught by Cade, one of ordinary skill in the art would utilize/modify the above teaching to obtain the doped semiconductor has a dopant concentration of 1019 cm-3, 1020 cm-3, 5x1020 cm-3 or 1021 cm-3 & to obtain the transmittance of the laser radiation that is less than or equal to one of 40 %, 20 %, 15 %, 10 %, 5 %, or 2 % as claimed, because dopant concentration/transmittance of laser radiation of a semiconductor layer depended on many variable parameters such as thickness, material, desired device requirement, dopant, surrounding layers, temperature, pressure, etc., and are known to affect device properties and would depend on the desired device density and the desired device characteristics. One of ordinary skill in the art would have been led to the recited concentration/transmittance through routine experimentation to achieve desired characteristics of the formed device.
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Cade in combination Endo/Stuber due to above reason.
Re claim 12, in combination cited above, Cade teaches the laser radiation is infra-red radiation (col. 3, 2nd par.).
Re claim 13, in combination cited above, Cade teaches the protective layer has a transmittance of laser radiation that is less than a transmittance of laser radiation in the substrate (abstract, col. 1, lines 45-52 & last par.).
Response to Arguments
4. Applicant's arguments with respect to claims have been considered but are moot in view of the new ground(s) of rejection. Response to arguments on newly added limitations are responded to in the above rejection.
Double Patenting over the claims is currently withdrawn due to claimed amendment.
Conclusion
5. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY T.V. NGUYEN whose telephone number is (571)270-7431. The examiner can normally be reached Monday-Friday, 7AM-4PM, alternative Friday off.
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/DUY T NGUYEN/Primary Examiner, Art Unit 2818 4/8/26
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