DETAILED ACTION
This office action is in response to Application No. 18/299,427, filed on 12 April 2023. Claims 1-20 are pending.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 17-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to abstract mental processes without significantly more. The claim(s) recite(s) a mapping method comprising steps of identifying core devices that meet core domain design rules, identifying an input/output circuit that meats input/output domain design rules, and mapping the input/output circuit into a modified circuit including core devices that meet the input/output domain design rule, which is an abstract design process that could be performed by a human in the mind or with pen and paper. Claims 18-20 merely recite additional design characteristics of the mapping, which do not change the abstract nature of the method.
This judicial exception is not integrated into a practical application because the only additional limitation aside from the abstract idea itself is activating a circuit analysis module, which is merely generic computer implementation that does not qualify as integration into a practical application. Similarly, the claim(s) does/do not include additional elements that are sufficient to amount to significantly more than the judicial exception because generic computer implementation does not amount to ‘significantly more’.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 2, 5-11, 14, and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Annema (“5.5-V I/O in a 2.5-V 0.25-um CMOS Technology”) in view of Parris (US 2020/0342070).
Regarding claim 1, Annema discloses an integrated circuit, comprising: a core domain having at least one core domain design rule limitation of a smaller device and a lower operating voltage; an input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain and a higher operating voltage than the lower operating voltage of the core domain (p. 528, col. 1, § I, ¶2); and a mapping cell that includes two or more electrical devices that each meet the at least one core domain design rule limitation, wherein the mapping cell is configured to be an input/output device and operate in the input/output domain at the higher operating voltage of the input/output domain (p. 528, col. 1, § I, ¶2 and col. 2, ¶1).
If Annema is found to be unclear regarding the core domain having at least one core domain design rule limitation of a smaller device; and the input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain, these features are well-known, as taught by Parris (¶25). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Annema and Parris, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using standard transistors in larger I/O domains. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Annema discloses using standard transistors from a chip process to form higher-voltage I/O circuits to interface with, e.g., ICs from previous (larger) generations. Parris teaches that the I/O has larger design limitations than the chip. The teachings of Parris are directly applicable to Annema in the same way, so that Annema would similarly use standard chip transistors to form higher-voltage I/O circuits in a larger I/O domain.
Regarding claim 2, Annema discloses that the mapping cell includes a cascode protection device that meets the at least one core domain design rule limitation connected in series with a core device that meets the at least one core domain design rule limitation (p. 528, col. 1, § I, ¶2 and col. 2, ¶1; p. 530, Fig. 2).
Regarding claim 5, Annema discloses that the mapping cell includes a cascode protection device that meets the at least one core domain design rule limitation connected in series with two or more core devices that meet the at least one core domain design rule limitation (p. 531, Fig. 3).
Regarding claim 6, Annema discloses that the mapping cell includes two or more cascode protection devices that meet the at least one core domain design rule limitation connected in series with a core device that meets the at least one core domain design rule limitation (p. 531, Fig. 3).
Regarding claim 7, Annema does not appear to explicitly disclose that the mapping cell is configured to operate in an analog application; Parris discloses these limitations (¶26). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Annema and Parris, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using standard transistors for I/O in chips of different applications. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Annema teaches using standard transistors of a chip to form high-voltage I/O circuits. Persons having ordinary skill in the art would recognize that chips are used in different applications such as analog or mixed-signal, as taught by Parris. The teachings of Parris are directly applicable to Annema in the same way, so that Annema would similarly used standard transistors for I/O in chips of different applications.
Regarding claim 8, Annema discloses that the mapping cell is configured to operate in one or more of a mixed signal application and a rail-to-rail application; Parris teaches these limitations (¶26). Motivation to combine remains consistent with claim 7.
Regarding claim 9, Annema discloses that each of the two or more electrical devices is an n-channel metal-oxide semiconductor field-effect transistor (p. 531, col. 1, ¶2).
Regarding claim 10, Annema discloses that each of the two or more electrical devices is a p-channel metal-oxide semiconductor field-effect transistor (p. 534, § A, ¶2; Fig. 9).
Regarding claim 11, Annema discloses a semiconductor circuit comprising: a core domain having at least one core domain design rule limitation of a smaller device and a lower operating voltage; an input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain and a higher operating voltage than the lower operating voltage of the core domain; a set of core devices that meet the at least one core domain design rule limitation; a core circuit that includes first core devices of the set of core devices; and an input/output circuit that includes second core devices of the set of core devices, wherein the input/output circuit operates at the higher operating voltage (p. 528, col. 1, § I, ¶2 and col. 2, ¶1). If Annema is found to be unclear regarding the core domain having at least one core domain design rule limitation of a smaller device; and the input/output domain having at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain, these features are well-known, as taught by Parris (¶25). Motivation to combine remains consistent with claim 1.
Regarding claim 14, Annema discloses that the second core devices include one core device connected in series to another core device (p. 530, Fig. 2).
Regarding claim 17, Annema discloses a mapping method comprising: activating a circuit analysis module; identifying core devices that meet at least one core domain design rule limitation of a smaller device and a lower operating voltage; and mapping the input/output circuit into a modified circuit that includes only the core devices such that the modified circuit meets the at least one input/output domain design rule limitation (p. 528, col. 1, § I, ¶2 and col. 2, ¶1).
Annema does not appear to explicitly disclose identifying an input/output circuit that meets at least one input/output domain design rule limitation of a larger device than the smaller device of the core domain and a higher operating voltage than the lower operating voltage of the core domain; Parris discloses these limitations (¶25). Motivation to combine remains consistent with claim 1.
Regarding claim 18, Annema discloses that mapping the input/output circuit into the modified circuit includes mapping each input/output device into two or more core devices that meet the at least one core domain design rule limitation, wherein the modified circuit operates in the input/output domain at the higher operating voltage (p. 530, Fig. 2).
Regarding claim 19, Annema discloses that mapping each input/output device into two or more core devices includes mapping each input/output device into a first core device that operates as a cascode protection device and a second core device that is connected in series to the first core device (p. 530, Fig. 2).
Claim(s) 3, 4, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Annema in view of Parris and Kumar (US 2013/0141140).
Regarding claim 3, Annema does not appear to explicitly disclose that the mapping cell includes a first input device connected to gates of the cascode protection device and the core device; Kumar discloses these limitations (Fig. 4). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Annema, Parris, and Kumar, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way, or the substitution of one device for a known equivalent, to achieve the predictable results of reducing Vds stress across cascaded devices. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Annema teaches cascoded I/O circuits. Kumar teaches cascoded I/O circuits with further reduced Vds stress. The teachings of Kumar are directly applicable to Annema in the same way, so that Annema would similarly implement cascoded I/O circuits with reduced Vds stress.
Regarding claim 4, Annema does not appear to explicitly disclose that the mapping cell includes a second input device connected to gates of the cascode protection device, the core device, and the first input device; Kumar discloses these limitations (Fig. 4). Motivation to combine remains consistent with claim 3.
Regarding claim 20, Annema discloses that mapping each input/output device into two or more core devices includes mapping each input/output device into a first core device that operates as a cascode protection device, a second core device that is connected in series to the first core device (p. 530, Fig. 2), but does not appear to explicitly disclose a third core device that is connected to each gate of the first core device and the second core device; Kumar discloses these limitations (Fig. 4). Motivation to combine remains consistent with claim 3.
Claim(s) 12, 13, 15, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Annema in view of Parris and Raghavan (US 2015/0162448).
Regarding claim 12, Annema discloses that the set of core devices includes front-end-of-line devices (p. 536, Fig. 12). If Annema is found to be unclear regarding these limitations, Raghavan discloses the same (¶20). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Annema, Parris, and Raghavan, because doing so would have involved merely the routine combination of known elements according to known techniques to produce merely the predictable results of using standard FEOL transistors for I/O circuits. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1395. Annema discloses an I/O circuit comprises standard transistor. Persons having ordinary skill in the art, reading Annema, would understand that Annema’s transistors include FEOL devices, as taught by Raghavan. The teachings of Raghavan are directly applicable to Annema in the same way, so that Annema would similarly use standard FEOL transistors for I/O circuits.
Regarding claim 13, Annema does not appear to explicitly disclose that the set of core devices includes back-end-of-line devices; Raghavan discloses these limitations (¶7). It would have been obvious to persons having ordinary skill in the art before the effective filing date of the application to combine the teachings of Annema, Parris, and Raghavan, because doing so would have involved merely the routine use of a known technique to improve similar devices in the same way to achieve the predictable results of using BEOL transistors to reduce area and IR losses. KSR Int’l Co. v. Teleflex Inc., 82 U.S.P.Q.2d 1385, 1396. Annema teaches a circuit comprising transistors. Raghavan teaches that using BEOL transistors reduces area and IR losses. The teachings of Raghavan are directly applicable to Annema in the same way, so that Annema would similarly use BEOL transistors to reduce area and IR losses.
Regarding claim 15, Annema discloses that the one core device and the other core device are located on a same plane in the semiconductor circuit (p. 536, Fig. 12). If Annema is found to be unclear regarding these limitations, Raghavan discloses the same (¶20). Motivation to combine remains consistent with claim 12.
Regarding claim 16, Annema does not appear to explicitly disclose that the one core device and the other core device are located on different planes in the semiconductor circuit; Raghavan discloses these limitations (¶7). Motivation to combine remains consistent with claim 13.
Conclusion
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18 April 2026
/ARIC LIN/ Examiner, Art Unit 2851