DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-10 and 29 in the reply filed on 1/16/26 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5 and 6-8 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karnezos (US pat 7394148).
With respect to claim 1, Karnezos teaches a semiconductor package, comprising (see figs. 1-28, particularly fig. 2 and associated text):
a first redistribution wiring layer 112;
a first semiconductor device 114,144 on an upper surface (top) of the first redistribution wiring layer;
a first sealing member 217 on the first semiconductor device; a second redistribution wiring layer 12 on the first sealing member, such that a peripheral region of a lower surface of the second redistribution wiring layer is free of the first sealing member;
at least one second semiconductor device 214,244 on an upper surface of the second redistribution wiring layer; and
a plurality of bonding wirings 218 electrically connecting first redistribution connection pads (bottom exposed metal of 112) on a lower surface of the first redistribution wiring layer and second redistribution connection pads (bottom exposed metal of 12) on the peripheral region of the lower surface of the second redistribution wiring layer.
With respect to claim 2, Karnezos teaches the first redistribution connection pads are in a peripheral region of the first redistribution wiring layer. See fig. 2 and associated text.
With respect to claim 3, Karnezos teaches a second sealing member 207 on an outer region of the lower surface of the second redistribution wiring layer and on the plurality of bonding wires. See fig. 2 and associated text.
With respect to claim 4, Karnezos teaches a third sealing member on the upper surface of the second redistribution wiring layer and on the at least one second semiconductor device. See fig. 2 and associated text.
With respect to claim 5, Karnezos teaches the first semiconductor device is connected to the first redistribution wiring layer via conductive bumps (connector at end of wire) that are formed on first chip pads provided on an active surface of the first semiconductor device. See fig. 2 and associated text.
With respect to claim 6, Karnezos teaches external connection redistribution pads 318 on first redistribution pads on the lower surface of the first redistribution wiring layer. See fig. 2 and associated text.
With respect to claim 7, Karnezos teaches the external connection redistribution pads are on a central region of the first redistribution wiring layer. See fig. 2 and associated text.
With respect to claim 8, Karnezos teaches an adhesive member 113,103 between the first sealing member and the second redistribution wiring layer. See fig. 2 and associated text.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karnezos (US pat 7394148).
With respect to claim 9, Karnezos teaches the wiring is made of metal but fail to the wiring is made of copper.
However, the use of copper wiring is extremely well-known in semiconductor art.
Claim(s) 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karnezos (US pat 7394148).
With respect to claim 20, Karnezos teaches a semiconductor package, comprising (see figs. 1-28, particularly fig. 2 and associated text):
a first sub-package having a first upper surface (top) and a first lower surface (bottom) opposite to each other, the first sub-package having a first redistribution wiring layer 112 having a plurality of first redistribution connection pads (exposed bottom connectors of 112) exposed from the first lower surface, a first semiconductor device 114,144 on the first redistribution wiring layer and a first sealing member 217on the first semiconductor device;
a second sub-package having a second upper surface (top) and a second lower surface (bottom) opposite to each other, the second sub-package having a second redistribution wiring layer 12 having a plurality of second redistribution connection pads (bottom exposed metal of 12) and external connection redistribution pads exposed from the second lower surface, a second semiconductor device 214, 244 mounted on the second redistribution wiring layer, and a second sealing member 227 on the second semiconductor device;
an adhesive member 113, 103 between the first upper surface of the first sub-package and the second lower surface of the second sub-package to bond the first and second sub-packages;
a plurality of first bonding wirings 218 electrically connecting the first and second redistribution connection pads to each other; and external connection bumps 318 on the external connection redistribution pads, respectively.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Examiner’s Cited References
The cited references generally show the similar or related structure having stacked bottom structure and top structure and the bottom structure having a first bottom interconnect and a first top die and the top structure having a second bottom interconnect and a second top die, where the exposed lower surfaces of the first bottom interconnect and second bottom interconnect are interconnected as presently claimed by applicant.
Conclusion
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LONG . PHAM
Examiner
Art Unit 2823
/LONG PHAM/Primary Examiner, Art Unit 2897