DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant's election with traverse of Group I, claims 1-9, in the reply filed on 1/20/2026 is acknowledged. The traversal is on the ground(s) that a search of the product of Group I would invariably encompass Group II as the groups are inextricably linked in that both Groups involve the same configuration of a semiconductor device as described above. The restriction has not been shown to be proper since it has been shown that the requisite showing of serious burden has not been made. This is not found persuasive because, as stated in the Office action mailed 11/20/2025 , the product can be made by other processes that encompass different subject matter than what is claimed in the process claims. As such, the search for the product does not have to be solely confined to the area where the process would be searched, or even at all, as the product requires searching in the product areas of the classification scheme and the process requires searching in the process areas of the classification scheme and the search strategies used to search the different ways in which the product can be formed does not necessarily overlap in scope with the exact process steps claimed. Therefore, the Examiner has demonstrated in the Office action mailed 11/20/2025, and repeated herein, that the groups are independent or distinct due to the different processes that can be used to form the product that do not overlap with the claimed process and there is a serious search and/or examination burden due to the different processes that can be used (one specifically mentioned in the Office action mailed 11/20/2025) to form the product. The requirement is still deemed proper and is therefore made FINAL. Claim s 10-17 withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected group , there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/20/2026 . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-9 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Venkatraman et al (US 2013/0221428 and Venkatraman hereinafter) . As to claims 1-9: Venkatraman discloses [claim 1] a trench-gate semiconductor device (Fig. 8) , the semiconductor device comprising one or more unit cells (one unit cell is defined as one gate trench and a surrounding contact trench/moat as shown) arranged in a semiconductor region (comprising 102 and 105; [0024]) , wherein each unit cell comprises: a trench (222; [0028]) ; a first oxide layer ( 502 on sidewalls of 222, 502 can be an oxide; [00 34 ]) arranged on an upper portion of a side wall of the trench (222) , the first oxide layer ( 502 on sidewalls of 222 ) forming a gate oxide (gate dielectric that can be an oxide; [0034]) of the unit cell; a second oxide layer (322 can be an oxide; [0029]) arranged on a lower portion of the side wall and on a bottom of the trench (222) ; a first polysilicon region (542 can be the same material as 342, which can be polysilicon; [0034]-[0035] and [0030]-[0032]) arranged inside the trench (222) , separated from the upper portion of the side wall by the first oxide layer ( 502 on sidewalls of 222 ) , the first polysilicon region (542) forming a gate ([0034]) of the unit cell; a second polysilicon region (442 is formed from the same material as 342, which can be polysilicon; [0030]-[0032]) arranged inside the trench (222) , separated from the lower portion of the side wall and from the bottom of the trench by the second oxide layer (322) , the second polysilicon region (442) forming a buried source (442 is electrically connected to 342 and 846, which can be electrically connected to 842, which is connected to a source terminal, therefore, 442 is at the same potential as the source terminal and is a buried source; [0044]-[0046]) of the unit cell; a third oxide layer (502 between 542 and 342 ) arranged in between the first polysilicon region (542) and the second polysilicon region (442) ; a body region (602; [0037]) of a first charge type (opposite to that of layer 105; [0037]) , wherein the body region (602) is separated from the first polysilicon region (542) by the first oxide layer ( 502 on sidewalls of 222 ) ; and a first distance d1 from a top surface (107; [0037]) of the semiconductor region (105) to a bottom surface of the body region (602) is equal to or less than 3 microns (0.2 microns to 1.2 microns; [0037]) , and a second distance d2 from the top surface (107) of the semiconductor region (105) to a bottom surface of the first polysilicon region (542) extends at least 0.3 microns beyond the bottom surface of the body region (the top of the conductive structure 442 measured from the top surface 107 of the semiconductor region 105 is 0.45 microns to 1.3 microns below the top surface 107, the thickness of the third oxide 502 is 0.011 microns to 0.13 microns (11 nm to 130 nm), therefore, the top surface of the third oxide on the top surface of the conductive structure 442 can range from 0.32 microns to 1.289 microns (taking the minimum 0.011 microns from the maximum 1.3 microns to get the upper limit and taking the maximum 0.13 microns from the minimum 0.45 microns to get the lower limit), which corresponds to the depth of the bottom surface of the first polysilicon region 542 from the top surface 107 of the semiconductor region 105 as the bottom of the first polysilicon region 542 sits on the top surface of the third oxide 502 on the top surface of 442; [0032] and [0037]) ; [claim 2] wherein the trench (222) comprises a first trench (upper portion of 222) and a second trench (bottom portion of 222) extending from a bottom of the first trench (upper portion of 222) ; wherein the upper portion (where 502 is formed) corresponds to a side wall of the first trench (upper portion of 222) , and wherein the lower portion (where 322 is formed) corresponds to a side wall of the second trench (lower portion of 222) ; wherein the first polysilicon region (542) is arranged inside the first trench (upper portion of 222) , and wherein the second polysilicon region (442) is arranged inside the second trench (lower portion of 222) ; [claim 3] wherein each of the first (502 on sidewalls of 222) , second (322) and third (portion of 502 between 542 and 442) oxide layers jointly form a contiguous oxide region (as 502 and 322 can both be oxides and they are directly contacting each other, they are interpreted to be a contiguous oxide) ; [claim 4] wherein the semiconductor region (comprising 102 and 105) is formed by a semiconductor substrate (102) of a second charge type different from the first charge type ([0024]-[0026] and [0037]) , and an epitaxial layer (105) of the second charge type ([0024]-[0026]) arranged on top of the semiconductor substrate (102) , wherein the epitaxial layer (105) has a dopant concentration that is less than a dopant concentration of the semiconductor substrate (102 can be heavily doped and 105 can be moderately doped, which is less than the heavily doped range; [0024]-[0025]) , and wherein the first trench (upper portion of 222) and the second trench (lower portion of 222) are arranged only in the epitaxial layer (105) of the semiconductor region (comprising 105 and 102) ; [claim 5] wherein the one or more unit cells further comprise a source region (622; [0037]) of the second charge type ([0038]) , wherein the source region (622) vertically extends from a top surface (107) of the semiconductor region (105) to the body region (602) ; wherein the dopant concentration of the source region is greater than that of the epitaxial layer (the source regions are heavily doped, which is higher doping than 105; [0024]-[0026] and [0038]) ; and wherein: each unit cell further comprises a moat region (leftmost contact opening at the bottom of which 702 is formed; [0040]) arranged centrally, in between the first (upper portion of leftmost 222) and second trench (lower portion leftmost 222) of the corresponding unit cell and a first (upper portion of third from the left 222) and second trench (lower portion of third from the left 222 ) of an adjacent unit cell; the moat region (leftmost contact opening at the bottom of which 702 is formed ) is spaced apart from the first (upper portion of third from the left 222) and second trench ( lower portion of third from the left 222) of the corresponding unit cell; and the moat region (leftmost contact opening at the bottom of which 702 is formed) is formed by an etch through the source region into the body region (this is a product-by-process limitation and is given little patentable weight, see MPEP 2113; as the structure in Venkatraman is the same as the claimed structure, the claimed limitation is taught ) ; [claim 6] wherein the one or more unit cells further comprise a fourth oxide layer (fourth oxide is lower half of 722, 722 can be an oxide; [0040]) arranged on top of the first trench (upper portion of 222) and the source region (622) , and a fifth oxide layer (upper half of 722, 722 can be an oxide, claim doesn’t establish a structural or material difference between the fourth and fifth oxides so Examiner interprets they can be different regions of the same material layer) arranged on top of the fourth oxide layer (lower half of 722) ; [claim 7] wherein the one or more unit cells are identical to one another (as shown, there are a plurality of identical unit cells) ; and/or wherein the second distance d2 extends between 0.3 microns and 0.8 microns beyond the bottom surface of the body region; and/or wherein the first trench has a depth relative to a top surface of the semiconductor region that lies in a range between 0.5 and 2.0 microns; and/or wherein the second trench has a depth relative to the bottom of the first trench that lies in a range between 0.2 and 2.0 microns; and/or wherein the first polysilicon region and/or the second polysilicon region has a width that lies in a range between 0.1 and 2.0 microns; and/or wherein the semiconductor region (comprising 102 and 105) comprises a silicon-based semiconductor body (105 can be silicon based; [0025]) ; and/or wherein the first oxide layer, the second oxide layer and the third oxide layer comprise silicon dioxide; and/or wherein the semiconductor device is a trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) (the structure is a trench gate MOSFET; [0023]) ; [claim 8] wherein each of the first (502 on sidewalls of 222) , second (322) and third (portion of 502 between 542 and 442) oxide layers jointly form a contiguous oxide region (as 502 and 322 can both be oxides and they are directly contacting each other, they are interpreted to be a contiguous oxide) ; [claim 9] wherein the semiconductor device further comprises a metal layer (842; [0044]-[0046]) arranged on top of at least one of the one or more unit cells of the semiconductor device, and wherein the metal layer (842) is configured to provide a source contact ([0046]) for the one or more unit cells, to electrically contact the body region (602) , and electrically connect the source region (622) to the buried source ( 442 ; 442 is electrically connected to 342 and 846, which can be electrically connected to 842, which is connected to a source terminal, therefore, 442 is at the same potential as the source terminal and is a buried source; [0044]-[0046] ) ; wherein the semiconductor device further comprises a metal contact (844; [0044]-[0046]) arranged on top of the first polysilicon region (542) of at least one of the one or more unit cells and configured to provide a gate contact ([0046]) for the one or more unit cells, and wherein the metal contact (844) is arranged at or near an end of the one or more unit cells where the metal layer (842) is absent. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT JOSEPH C NICELY whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-3834 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 7:30 am - 4 pm, EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Steven Gauthier can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-0373 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent- center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. FILLIN "Examiner Stamp" \* MERGEFORMAT JOSEPH C. NICELY Primary Examiner Art Unit 2813 /JOSEPH C. NICELY/ Primary Examiner, Art Unit 2813 3/25/2026