DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Election/Restrictions
Applicant’s election without traverse of Group-I in the reply filed on 07/22/2026 is acknowledged.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7 and 15-20 are rejected under 35 U.S.C. 35 U.S.C. 103 as being unpatentable over Kittl et al. (US PGPub: 2017/0271514 A1), hereinafter Kittl, in view of KIM et al. (US PGPub: 2017/0053998 A1), hereinafter KIM
Regarding claim 1, Kittl teaches a semiconductor structure comprising:
a gate cut structure (FIG. 3A-4H) comprising a first region, a second region, a dielectric liner (427), and a dielectric filler (415); the first region being between a first and a second gate of a first and a second transistor respectively; the second region being between a first and a second source/drain region of the first and the second transistor respectively; and the dielectric liner (427) surrounding the dielectric filler at a bottom and sidewalls of the dielectric filler in the first and the second region,
wherein the dielectric filler(415) has a first height and the dielectric liner (427) in the first region between the first and the second gate of the first and the second transistor has a second height, and the second height is smaller than the first height.
Kittl does not explicitly teach second height is smaller than first height.
However it is taught in KIM that a spacer material which is considered dielectric liner has a height smaller than dielectric filler 210 or 332. These layers made out of low-k dielectric materials (having a dielectric constant less than 3.6, paragraph [0034], [0029], [0045])
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Kittl’s semiconductor structure with other teaching from KIM in order to meet improve device functionality by using dielectric filler, liner low-k material so that device performance improves.
Regarding claim 2, Kittl teach the semiconductor structure of claim 1, wherein the dielectric liner in the second region between the first and the second source/drain region of the first and the second transistor has a third height and a fourth height, wherein the third height of the dielectric liner is substantially same as the first height of the dielectric filler (414) (414 having the fourth height is directly below a first source/drain contact of the first transistor. the third/fourth height can be any height of 414 which is underneath source/drain electrode 423, 424).
Regarding claim 3, Kittl teaches the semiconductor structure of claim 2, wherein the fourth height is smaller than the third height and a portion of the dielectric liner having the fourth height is directly below a first source/drain contact of the first transistor (414 having the fourth height is directly below a first source/drain contact of the first transistor the third/fourth height can be any height of 414. which is underneath source/drain electrode 423, 424).
Regarding claim 4, Kittl teaches the semiconductor structure of claim 3, further comprising a dielectric cap (429) above the first and the second metal gate (428) of the first and the second transistor, wherein the dielectric cap is planarized to has a top surface that is co-planar with a top surface of the dielectric filler (dielectric filler 450 and 429 is coplanar) and has a fifth height that is substantially same as the first height of the dielectric filler and substantially same as the third height of the dielectric liner (these height are subject to interpretation and can be manipulated to change the length/height in order to fit device functionality.).
Regarding claim 5, Kittl teaches the semiconductor structure of claim 4, wherein the dielectric cap (429) is directly on top of the dielectric liner between the first and the second gate of the first and the second transistor, the dielectric cap has an etch selectivity (layers 415, 416 may include a task of performing an anisotropic etch to selectively remove any conductive passivation material on the portions 419, 420 of the substrate 404. Paragraphs [0040]-[0046], abstract, [0037]) that is different from an etch selectivity of the dielectric filler and different from an etch selectivity of the dielectric liner (etch selectivity can be different and it is subject to alter depending on material selection).
Regarding claim 6, Kittl teaches (in view of KIM) the semiconductor structure of claim 1, wherein the first and the second transistor include low-k spacers (413) at sidewalls of the first and the second metal gate (406) respectively, and the dielectric liner (427) is a low-k dielectric material that is substantially same as the low-k spacers.
Regarding claim 7, Kittl teaches the semiconductor structure of claim 1, wherein the dielectric filler has an etch selectivity that is different from an etch selectivity of the dielectric liner (etch selectivity can be different and it is subject to alter depending on material selection) and is substantially same materially as an interlevel dielectric layer on top of the first and the second source/drain region of the first and the second transistor (layers 415, 416 may include a task of performing an anisotropic etch to selectively remove any conductive passivation material on the portions 419, 420 of the substrate 404. Paragraphs [0040]-[0046], abstract, [0037]).
Regarding claim 15, Kittl teaches a semiconductor structure comprising:
a gate cut structure having a first region between a first and a second metal gate of a first and a second transistor respectively and a second region between a first and a second source/drain region of the first and the second transistors respectively; the gate cut structure including a dielectric liner and a dielectric filler, the dielectric liner surrounding the dielectric filler at a bottom and sidewalls thereof,
wherein the dielectric filler has a first height, and the dielectric liner has a second height in the first region and a third and a fourth height in the second region, wherein the second height is smaller than the first height, the third height is substantially same as the first height, and the fourth height is smaller than the third height.
Kittl does not explicitly teach second height is smaller than first height.
However it is taught in KIM that a spacer material which is considered dielectric liner has a height smaller than dielectric filler 210 or 332. These layers made out of low-k dielectric materials (having a dielectric constant less than 3.6, paragraph [0034], [0029], [0045])
Hence, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use Kittl’s semiconductor structure with other teaching from KIM in order to meet improve device functionality by using dielectric filler, liner low-k material so that device performance improves.
Regarding claim 16, Kittl teaches the semiconductor structure of claim 15, wherein a portion of the dielectric liner (414) having the fourth height is directly below a first source/drain contact of the first transistor (the fourth height can be any height of 414. which is underneath source/drain electrode 423, 424).
Regarding claim 17, Kittl teaches the semiconductor structure of claim 16, further comprising a dielectric cap (429) above the first and the second metal gate (428) of the first and the second transistor, wherein the dielectric cap is planarized to has a top surface that is co-planar with a top surface of the dielectric filler (dielectric filler 450 and 429 is coplanar).
Regarding claim 18, Kittl teaches the semiconductor structure of claim 17, wherein the dielectric cap (429) is directly on top of the dielectric liner in the first region between the first and the second gate (428) of the first and the second transistor, the dielectric cap comprises a dielectric material that enables a selective etching process relative to the dielectric filler and the dielectric liner (the gate stacks 323 include dielectric capping layers 327, such as nitrides … Paragraph [0037], [0025], [0047]).
Regarding claim 19, Kittl teaches (in view of KIM) the semiconductor structure of claim 15, wherein the first and the second transistor include low-k spacers (413) at sidewalls of the first and the second metal gate (406) respectively, and the dielectric liner (427) is a low-k dielectric material that is substantially same as the low-k spacers.
Regarding claim 20, Kittl teaches the semiconductor structure of claim 15, wherein the dielectric filler has an etch selectivity that is different from an etch selectivity of the dielectric liner (etch selectivity can be different and it is subject to alter depending on material selection) and is substantially same as an etch selectivity of an interlevel dielectric layer on top of the first and the second source/drain region of the first and the second transistor (layers 415, 416 may include a task of performing an anisotropic etch to selectively remove any conductive passivation material on the portions 419, 420 of the substrate 404. Paragraphs [0040]-[0046], abstract, [0037])
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See form PTO-892.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHEIKH MARUF whose telephone number is (571)270-1903. The examiner can normally be reached M-F, 8am-6pm EDT.
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/SHEIKH MARUF/Primary Examiner, Art Unit 2897
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