DETAILED ACTION
This office action is in response to applicant’s amendment filed on December 17, 2025. Claims 1-2, 5-18, and 20-23 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 16-18 and 20-21 are rejected under 35 U.S.C. 103 as being unpatentable over Dawnay as in view of Boukai et al.(US 2020/0388743 A1, herein “Boukai”).
Regarding claim 16, Dawnay discloses a method for forming a photonic device, comprising:
forming a first waveguide (4) on a substrate (10);
forming a second waveguide (3) on the substrate (10), wherein a segment of the second waveguide is laterally offset a segment of the first waveguide (Fig. 1);
forming a first thermoelectric structure (6) within the substrate having a first doping type (n-doped);
forming a second thermoelectric structure (7) within the substrate having a second doping type opposite the first doping type (p-doped);
forming a heater structure (8’ or 8”) of over the segment of the first waveguide (4); and
forming a cooler structure over the segment of the second waveguide (3), wherein the first and second thermoelectric structures are electrically coupled between the heater structure and the cooler structure (via n-doped region and p-doped region);
depositing a first dielectric layer over the substrate (silicon dioxide 12 on substrate 11 in Fig. 2a).
Dawnay does not teach etching the first dielectric layer to form a plurality of openings in the first dielectric layer; forming a plurality of conductive contacts in the plurality of openings, wherein the plurality of conductive contacts comprise a first pair of conductive contacts on opposite sides of the first thermoelectric structure and a second pair of conductive contacts on opposing sides of the second thermoelectric structure.
Boukai teaches etching through a semiconductor substrate to produce holes in the substrate (Para [0112]) and depositing metallic particles to form array of rod-like structure or wires (Fig. 6, Para [0017], [0071], [0093], [0110]-[0112]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention for Dawnay to etch openings in the dielectric layer (SiO2) and deposit metallic material to form the vias for sending a current to control the thermoelectric structure. Furthermore, it is within the skill of the practitioner in the art to employ masks to accurately etch the placement of the vias for providing currents through the thermoelectric structure to controlling the heating of the structure. One would be motivated to employ Boukai’s etching method since etching is widely known semiconductor manufacturing technique.
Regarding to claim 17, Dawnay teaches the method of claim 16, but Dawnay does not teach using ion implantation process to form the first and second thermoelectric structure within the substrate.
Boukai teaches forming a thermoelectric structure on a substrate using ion implantation to dope regions with P or N dopants (Para [0127]).
Regarding claim 18, Boukai further teaches depositing one or more thermoelectric materials over an upper surface of the substrate (“dopant atoms are injected into the semiconductor substrate”, Para [0127]); performing one or more implantation process on the one or more thermoelectric materials (“ions of a material (e.g., NH3 or B2H6) are accelerated in an electrical field and impacted into the semiconductor substrate”, Para [0127]); and performing a patterning process on the one or more thermoelectric materials (Para [0129]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention for Dawnay to use ion implantation to form both the first and second thermoelectric structures and patterning to form holes such as vias for electrical interconnections. Ion implantations and patterning are well known techniques use to dope semiconductor materials to have electrical properties and the method is also effective for controlling precise level of dopants on an area. This allows the thermoelectric to be fabricated using a precise method to control the levels of dopants which will result in a higher quality device.
Regarding claims 20-21, Dawnay in view of Boukai teach the method of claim 16, but Dawnay in view of Boukai do not teach the heater structure and the cooler structure are formed concurrently with one another. Nor does Dawnay in view of Boukai teach the plurality of conductive contacts are formed before the heater structure and the cooler structure.
The examiner considers the limitations of “concurrently formed with one another” to be an obvious step in view of KSR “obvious to try”. In this particular case the possible outcomes result in 2 scenarios. 1) to form them concurrently or 2) to form them separately; since the possible outcomes are finite and one can test both outcomes in the two process steps to see which will produce a faster manufacturing time. The results are hence predictable and can be reasonably discover without many trials. Thus, one of ordinary skill would be motivated to try to discover the fastest way to produce the device in order to increase manufacturing yield (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 [2007]). As for the step of conductive contacts are formed before the heater structure and the cooler structure would have been obvious since the cooler and heater structure are the last layer deposited on the substrate 11 as shown in Dawnay.
Allowable Subject Matter
Claims 1-2, 5-9, 10-15, and 22-23 allowed.
The following is an examiner’s statement of reasons for allowance: the prior arts of record do not teach all the limitations of claim 1 and claim 10, as amended.
The prior arts do not teach claim 1, specifically, a first conductive contact vertically extending from the first conductive structure to the first thermoelectric structure, wherein the first conductive contact is spaced between outer sidewalls of the first conductive structure and has a width that is less than a lateral distance between the first conductive contact and the segment of the first waveguide.
The prior arts do not teach claim 10, specifically, a first conductive cooler structure overlying the second waveguide segment and laterally offset from the first and second conductive heater structures in a second direction orthogonal to the first direction, wherein the first conductive cooler structure comprises a first curved sidewall laterally offset from a second curved sidewall, wherein the second waveguide segment is spaced between the first and second curved sidewalls.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claims 16-18, and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Erin D Chiem whose telephone number is (571)272-3102. The examiner can normally be reached 10 am - 6 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thomas A. Hollweg can be reached at (571) 270-1739. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIN D CHIEM/Examiner, Art Unit 2874
/THOMAS A HOLLWEG/Supervisory Patent Examiner, Art Unit 2874
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