Prosecution Insights
Last updated: May 29, 2026
Application No. 18/300,638

LATERAL COILS USED FOR ENERGY TRANSFER OVER ISOLATION REGION IN MULTI-VOLTAGE DEVICES

Non-Final OA §103
Filed
Apr 14, 2023
Examiner
TIVARUS, CRISTIAN ALEXANDRU
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Infineon Technologies AG
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
3m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
28 granted / 36 resolved
+9.8% vs TC avg
Strong +19% interview lift
Without
With
+18.9%
Interview Lift
resolved cases with interview
Typical timeline
3y 4m
Avg Prosecution
24 currently pending
Career history
83
Total Applications
across all art units

Statute-Specific Performance

§103
86.6%
+46.6% vs TC avg
§102
8.0%
-32.0% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 36 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election with traverse of Group I, corresponding to claims 1-5 and 12-19, drawn to product, in the reply filed on 01/28/2026, is acknowledged. At the examiner discretion, and as requested by the applicant, claims 1-8 and 12-19 corresponding to Species 1-3 will be examined. All the other restriction requirements regarding Species 4, represented by figure 6, Species 5 represented by figure 7, and Species 6 represented by figure 8, as listed in the Requirement for Restriction office action filed on 01/15/2026, remain as listed. The restriction is final. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-5, 12-19 are rejected under 35 U.S.C. 103 as being unpatentable over Miyagawa (United States Patent Application Publication, US 2016/0365316 A1), hereinafter referenced as Miyagawa, in view of disclosed prior art, Grasso, (United States Patent Application Publication Number, US 2022/0020843 A1) hereinafter referenced as Grasso. Regarding claim 1, Miyagawa teaches a multi-voltage domain device, comprising: a circuit substrate comprising a first main surface and a second main surface arranged opposite to the first main surface (Fig.2, formed by element #102 and #104, first surface is top surface of element #104 and second surface is bottom surface of element #102), wherein the circuit substrate comprises: a first region comprising first circuitry that operates in a first voltage domain a second region comprising second circuitry that operates in a second voltage domain (Fig.16B, first circuitry region, element #110, second circuitry region, element #120, paragraph [0068], rows 1-4 and 11-14 are formed in element #104, paragraph [0069], rows 3-6), and an isolation region that electrically isolates the first region and the second region in a lateral direction that extends parallel to the first main surface and the second main surface (Fig.16B, element #520 is an insulator, paragraph [0102], rows 6-9, which fills the groove, element #500, extends in horizontal direction, has a width in that direction). Grasso also teaches an isolation region that electrically isolates two regions in a lateral direction in order to electrically isolate the first circuitry and the second circuitry, wherein the lateral direction extends parallel to the first main surface and the second main surface of the substrate (Fig.1A and 1B, isolation region, element #5, paragraph [0044], row 5, electrically isolates the circuitry from voltage domain A, from the circuitry from the voltage domain B, and extends in two directions parallel to main surface of the substrate, element #1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Grasso and disclose an isolation region that electrically isolates two region in a lateral direction in order to electrically isolate the first circuitry and the second circuitry, wherein the lateral direction extends parallel to the first main surface and the second main surface of the layer. Isolating circuits build in the same semiconductor layer using isolation regions, such as the deep trench isolation region, as disclosed by Grasso, is well known in the art. Having the deep trench isolation surround the circuitry on all sides provides electrical isolation from circuits located on all sides of the surrounded circuitry. Miyagawa further teaches an insulator layer arranged on the first main surface of the circuit substrate (Fig.2, formed by elements #106 and #108); a first coil arranged in the insulator layer wherein the first coil is electrically coupled to the first circuitry (Fig.2, element #112, paragraph [0068], rows 7-10), and is isolated from the second region (Fig.16B, elements #520 and #106 isolates the first coil from the second region, element #120. The isolation region disclosed by Grasso play the same role and extends in the direction corresponding to the horizontal direction of Fig.16B), wherein the first coil has a first center axis around which first windings of the first coil are wound (Fig.3A shows element #112 having vertical windings, the axis is in the center of winding, in a direction perpendicular to the vertical and horizontal direction of the figure) and wherein the first center axis extends parallel to the lateral direction (Fig.2 shows element #112 having multiple windings, and the center axis extends in the horizontal direction, paragraph [0066], rows 8-11); and a second coil arranged in the insulator layer and laterally separated from the first coil in the lateral direction by an insulator material of the insulator layer (Fig.2, element #122 also showed in Fig.16B, element #106 and #520 separates them. The isolation region disclosed by Grasso plays the same role and extends in the direction corresponding to the horizontal direction of Fig.16B), wherein the second coil is electrically coupled to the second circuitry (paragraph [0068], rows 7-10), and is isolated from the first region (Fig.16B, elements #520 and #106 isolate the second coil from the first region, element #110), wherein the second coil has a second center axis around which second windings of the second coil are wound (Fig.3A shows element #122 having vertical windings, the axis is in the center of winding, in a direction perpendicular to the vertical and horizontal direction of the figure), and wherein the second center axis extends parallel to the lateral direction and is aligned with the first center axis (Fig.2 shows element #122 having multiple windings, and the center axis extends in the horizontal direction, paragraph [0066], rows 8-12), wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction based on an alignment of the first center axis with the second center axis (Fig.2 and 3A, the coils are aligned so the axis are aligned, and magnetically coupled, paragraph [0008], rows 1-3, paragraph [0068], rows 19-22). Regarding claim 2, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the first center axis is collinear with a first magnetic axis of the first coil and the second center axis is collinear with a second magnetic axis of the second coil (Fig.2A and 3, given the geometry, symmetry and the orientation of the windings of the two coils, the center axes are collinear to the magnetic axes, see also Fig.20B). Regarding claim 3, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the insulator layer is a stack-insulator layer comprising a plurality of sub-insulator layers (Fig.2, element #106 is a multilayer interconnect layer), wherein the first coil comprises a first plurality of conductive layers and a first plurality of conductive vias integrated in the insulator layer, and wherein the second coil comprises a second plurality of conductive layers and a second plurality of conductive vias integrated in the insulator layer (Fig.2 and 3A, show the coils comprise conductive layers and vias). Regarding claim 4, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claims 1 and 3 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 3, wherein the first plurality of conductive vias extend vertically between first plurality of conductive layers, and the second plurality of conductive vias extend vertically between second plurality of conductive layers (Fig.2 and 3A shows vertical vias between conductive layers). Regarding claim 5, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the first coil and the second coil are encapsulated by the insulator material of the insulator layer (Fig.2 and 3A, the coils are encapsulated by elements #106 and #108). Regarding claim 12, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the isolation region comprises one or more trench isolation barriers, and wherein each of the one or more trench isolation barriers extends vertically from the first main surface to the second main surface (Fig.16B, element #520 fills a trench groove, element #500, extends between the top surface of element #106 and bottom surface of element #102. Grasso also teaches above limitations, element #5 in Fig.1B). Regarding claim 13, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the first coil comprises at least two first terminals that are arranged vertically over the first region and are electrically coupled to the first circuitry, and wherein the second coil comprises at least two second terminals that are arranged vertically over the second region and are electrically coupled to the second circuitry (Fig.20B, each coil has two terminals inside the layer #106, which is vertically above the corresponding circuits and the terminals are connected to corresponding circuits, paragraph [0106], rows 14-17). Regarding claim 14, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the first coil and the second coil are configured to utilize a magnetic coupling to transmit communication signals or power signals between the first circuitry and the second circuitry, over the isolation region (paragraph [0008], rows 1-3 and paragraph [0068], rows 19-22). Regarding claim 15, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 1, wherein the circuit substrate is a semiconductor substrate (paragraph [0069], rows 2-5. Grasso also teaches the circuit substrate, element #3 in Fig.1B is a semiconductor, paragraph [0039], rows 6-7). Regarding claim 16, Miyagawa teaches a multi-voltage domain device, comprising: a semiconductor layer comprising a first main surface and a second main surface arranged opposite to the first main surface (Fig.2, element #104, first surface is top surface and second surface is the bottom surface, paragraph [0069], rows 2-5), wherein the semiconductor layer comprises: a first region comprising first circuitry, a second region comprising second circuitry (Fig.16B, first circuitry region, element #110, second circuitry region, element #120, paragraph [0068], rows 1-4 and 11-14 are formed in element #104, paragraph [0069], rows 3-6), and an isolation region that electrically isolates the first region and the second region in a lateral direction in order to electrically isolate the first circuitry and the second circuitry, wherein the lateral direction extends parallel to the first main surface and the second main surface (Fig.16B, element #520 is an insulator, paragraph [0102], rows 6-9, which fills the groove 500, which extends in horizontal direction, has a width in that direction). Grasso also teaches an isolation region that electrically isolates two regions in a lateral direction in order to electrically isolate the first circuitry and the second circuitry, wherein the lateral direction extends parallel to the first main surface and the second main surface of the substrate (Fig.1A and 1B, isolation region, element #5, paragraph [0044], row 5, electrically isolates the circuitry from voltage domain A, from the circuitry from the voltage domain B, and extends in two directions parallel to main surface of the substrate, element #1). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Grasso and disclose an isolation region that electrically isolates two region in a lateral direction in order to electrically isolate the first circuitry and the second circuitry, wherein the lateral direction extends parallel to the first main surface and the second main surface of the layer. Isolating circuits build in the same semiconductor layer using isolation regions, such as the deep trench isolation region disclosed by Grasso, is well known in the art. Having the deep trench isolation surround the circuitry on all sides provides electrical isolation from circuits located on all sides of the surrounded circuitry. Miyagawa further teaches an insulator layer arranged on the first main surface of the semiconductor layer (Fig.2, formed by elements #106 and #108); a first coil arranged in the insulator layer, wherein the first coil is electrically coupled to the first circuitry (Fig.2, element #112, paragraph [0068], rows 7-10), and is isolated from the second region (Fig.16B, elements #520 and #106 isolates the first coil from the second region, element #120 The isolation region disclosed by Grasso play the same role and extends in the direction corresponding to the horizontal direction of Fig.16B), wherein the first coil has a first center axis around which first windings of the first coil are wound (Fig.3A shows element #112 having vertical windings, the axis is in the center of winding, in a direction perpendicular to the vertical and horizontal direction of the figure), wherein the first windings define a first core area of the first coil that extends along the first center axis, and wherein the first center axis extends parallel to the lateral direction (Fig.2 shows element #112 having multiple windings, that define a core area, and the center axis extends in the horizontal direction, paragraph [0066], rows 8-11); and a second coil arranged in the insulator layer and laterally separated from the first coil in the lateral direction by an insulator material of the insulator layer (Fig.2, element #122, also showed in Fig.16B, element #106 and #520 separates them. The isolation region disclosed by Grasso play the same role and extends in the direction corresponding to the horizontal direction of Fig.16B), wherein the second coil is electrically coupled to the second circuitry (paragraph [0068], rows 7-10) and is isolated from the first region (Fig.16B, elements #520 and #106 isolates the second coil from the first region, element #110, wherein the second coil has a second center axis around which second windings of the second coil are wound Fig.3A shows element #122 having vertical windings, the axis is in the center of winding, in a direction perpendicular to the vertical and horizontal direction of the figure), wherein the second windings define a second core area of the second coil that extends along the second center axis, and wherein the second center axis extends parallel to the lateral direction (Fig.2 shows element #122 having multiple windings, that define a core area, and the center axis extends in the horizontal direction, paragraph [0066], rows 8-11), wherein the first core area is at least partially aligned with the second core area in the lateral direction (Fig.2 shows the two core areas aligned in the horizontal direction), wherein the first coil and the second coil are magnetically coupled to each other in the lateral direction based on an alignment of the first core area with the second core area (paragraph [0008], rows 1-3 and paragraph [0068], rows 19-22). Regarding claim 17, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 16, as set forth in the obviousness rejection. Miyagawa does not teach the multi-voltage domain device of claim 16, further comprising: a wafer insulator layer comprising a third main surface, wherein the second main surface of the semiconductor layer is arranged at the third main surface of the wafer insulator layer, and wherein the isolation region includes at least one trench isolation barrier that extends vertically from the first main surface to the third main surface. Grasso teaches the multi-voltage domain device of claim 16, further comprising: a wafer insulator layer comprising a third main surface (Fig.1B, element #2 is an oxide as part of an SOI wafer, and top surface of element #2 is the third main surface), wherein the second main surface of the semiconductor layer is arranged at the third main surface of the wafer insulator layer (Fig.1B, bottom surface of element #3 is arranged at the top surface of element #2), and wherein the isolation region includes at least one trench isolation barrier that extends vertically from the first main surface to the third main surface (Fig.1B, element #5). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Grasso and disclose the multi-voltage domain device further comprising: a wafer insulator layer comprising a third main surface, wherein the second main surface of the semiconductor layer is arranged at the third main surface of the wafer insulator layer, and wherein the isolation region includes at least one trench isolation barrier that extends vertically from the first main surface to the third main surface. As a result of device miniaturization, the widths of the isolation regions are small and leakage can occur through the substrate, below the isolation regions. The wafer isolation layer prevents this leakage from occurring. Regarding claim 18, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claims 16 and 17, as set forth in the obviousness rejection. Grasso further teaches the multi-voltage domain device of claim 17, further comprising a silicon-on-insulator (SOI) wafer comprising the semiconductor layer and the wafer insulator layer (Fig.1B, element #1, #2 and #3 form an SOI wafer). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Grasso and disclose the multi-voltage domain device further comprising a silicon-on-insulator (SOI) wafer comprising the semiconductor layer and the wafer insulator layer. As a result of device miniaturization, the widths of the isolation regions are small and leakage can occur through the substrate, below the isolation regions. The SOI wafer prevents this leakage from occurring. Regarding claim 19, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 16, as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 16, wherein the multi- voltage domain device is a monolithic device (Fig.2, element #100 is a monolithic device). Claims 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Miyagawa in view of Grasso and in view of Loza et al., (United States Patent Application Publication Number, US 2008/0204183 A1) hereinafter referenced as Loza. Regarding claim 6, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1, as set forth in the obviousness rejection. The combination of Miyagawa and Grasso does not teach wherein the first coil has a first coil width, and wherein the second coil has a second coil width that is different from the first coil width. Loza teaches wherein the first coil has a first coil width, and wherein the second coil has a second coil width that is different from the first coil width (Fig.8, first coil width, element #801 is different from the second coil width, element #803, paragraph [0043], rows 1-4). ). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Loza and disclose wherein the first coil has a first coil width, and wherein the second coil has a second coil width that is different from the first coil width. As disclosed by Loza, this configuration can be used to build a transformer (paragraph [0044], rows 6-8), where the design of the coils is tailored based on the desired performance of the transformer. Regarding claim 7, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1, as set forth in the obviousness rejection, and the combination of Miyagawa, Grasso and Loza teaches the multi-voltage domain device of claim 6 as set forth in the obviousness rejection. Miyagawa further teaches the multi-voltage domain device of claim 6, wherein the first coil width is uniform or substantially uniform throughout the first coil, and wherein the second coil width is uniform or substantially uniform throughout the second coil (Fig.3A shows the equal windings, paragraph [0070], rows 5-7, see also Fig.20B). Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Miyagawa in view of Grasso and in view of Flemming et al., (United States Patent Application Publication Number, US 2023/0122085 A1) hereinafter referenced as Flemming. Regarding claim 8, the combination of Miyagawa and Grasso teaches the multi-voltage domain device of claim 1, as set forth in the obviousness rejection. The combination of Miyagawa and Grasso does not teach the multi-voltage domain device of claim 1, wherein at least one of the first coil or the second coil is a tapered coil having a respective tapered coil width that changes in the lateral direction. Flemming teaches a coil is a tapered coil having a respective tapered coil width that changes in the lateral direction (Fig.2). It would have been obvious to one ordinary skilled in the art, before the effective filing date of the claimed invention to incorporate the teachings of Flemming and disclose wherein at least one of the first coil or the second coil is a tapered coil having a respective tapered coil width that changes in the lateral direction. As disclosed by Flemming, tapered coils provide a broad frequency response as compared to other type of coils. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CRISTIAN A TIVARUS whose telephone number is (703)756-4688. The examiner can normally be reached Monday- Friday 8:00 AM -5:00 PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at (571)270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CRISTIAN A TIVARUS/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 14, 2023
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
97%
With Interview (+18.9%)
3y 4m (~3m remaining)
Median Time to Grant
Low
PTA Risk
Based on 36 resolved cases by this examiner. Grant probability derived from career allowance rate.

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