DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 11 is rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter as explained below.
Regarding the term “electronic memory encoded with data” in claim 11; the broadest reasonable interpretation of a claim drawn to an electronic memory encoded with data, as the claim presented, covers both forms of non-transitory tangible media and transitory propagating signals per se in view of the ordinary and customary meaning of computer readable media, including electronic memory, particularly when the specification is silent (see MPEP 2111.01). Because the broadest reasonable interpretation covers a signal per se, a rejection under 35 USC 101 is appropriate as covering non-statutory subject matter. See 1351 OG 212, Feb 23 2010.
The Examiner suggests that the Applicant replaces “electronic memory encoded with data” in claim 11 with --non-transitory electronic memory encoded with data--.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nardi et al., hereinafter Nardi, US Patent No. 10,853,545.
Regarding Claim 1, Nardi teaches a computer-implemented method of performing failure mode, effects and diagnostic analysis (FMEDA) (Nardi Col. 3, Lines 13-15, see design flow using FMEDA) on hardware IP of an electronic system, the method comprising:
accessing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model (Nardi Col. 4, Lines 56-67 and Col. 5, Lines 1-65, wherein an FS data structure including FS data is accessed, the FS data containing reliability and failure rate information, i.e. failure mode characterizations, and safety mechanisms, i.e. safety data, on components); and
compiling the safety library components and the hardware IP, including mapping instances of hardware models in the hardware IP to corresponding safety library components (Nardi Col. 2, Lines 39-43, Col. 7, Lines 1-14, and Col. 10, Lines 2-44, wherein the FS data is mapped to the circuit components) and aggregating the characterizations and safety data of the corresponding components (Nardi Col. 6, Lines 28-44 and Col. 11, Lines 18-20, wherein the FS data may be aggregated in a single file).
Regarding Claim 2, Nardi further teaches wherein each safety library component contains attributes and safety values (Nardi Col. 9, Lines 12-18, wherein the FS data contains attributes and values).
Regarding Claim 3, Nardi further teaches wherein each safety library component includes information for mapping to a hardware model (Nardi Col. 10, Lines 3-10, wherein mapping information is included in the FS data); and wherein mapping the library components to the IP blocks includes accessing the mapping information in the library components (Nardi Col. 7, Lines 1-12, wherein mapping utilizes the FS data).
Regarding Claim 4, Nardi further teaches generating global metrics from the aggregated characterizations and safety data (Nardi Col. 13, Lines 10-51, wherein metrics are generated using the FS data).
Regarding Claim 5, Nardi further teaches receiving a revised hardware IP (Nardi Col. 3, Lines 48-65, wherein modifications to the circuit design are performed); and
recompiling the safety library components and the revised hardware IP (Nardi Col. 7, Lines 31-53, wherein the FS data is remapped based on the modifications).
Regarding Claim 6, Nardi further teaches wherein the recompiling includes reusing components that are mapped to instances that have not changed in the revised hardware IP (Nardi Col. 7, Lines 31-53, wherein the FS data mapped to unchanged components remains in place).
Regarding Claim 7, Nardi further teaches wherein the recompiling includes demapping safety library components that correspond to instances that were removed from the revised hardware IP (Nardi Col. 6, Lines 55-67 and Col. 7, Lines 31-53, wherein the FS data mapped to changed components are modified, with removed components having removed FS data mapping).
Regarding Claim 8, Nardi further teaches wherein the recompiling includes demapping safety library components mapped to instances having revised functionality in the revised hardware IP, and mapping new safety library components to the instances having the revised functionality (Nardi Col. 7, Lines 31-53, wherein the FS data mapped to changed components are modified, with changed components having FS data updated which is demapping old FS data and mapping new FS data).
Regarding Claim 9, Nardi further teaches wherein each safety library component includes safety values and design data (Nardi Col. 10, Lines 4-44 and Col. 13, Lines 10-39, wherein the FS data includes safety information and design component information); and wherein the method further comprises extracting the safety values and design data to produce estimates of gate count and area (Nardi Col. 13, Lines 10-39, wherein the FS data is used to generate the number of gates and expected silicon area).
Regarding Claim 10, Nardi further teaches wherein the hardware IP blocks and the library are for a system--on-chip (Nardi Col. 10, Lines 25-26, wherein the design may be for an SOC).
Regarding Claim 11, Nardi teaches an article comprising electronic memory encoded with data (Nardi Col. 24, Lines 4-19, see memory), which when executed, causes a computing platform to perform failure mode, effects and diagnostic analysis (FMEDA) (Nardi Col. 3, Lines 13-15, see design flow using FMEDA) on hardware intellectual property (IP) of an electronics system, the FMEDA including the steps of:
referencing a library of safety library components, each safety library component containing failure mode characterizations and safety data about a hardware model (Nardi Col. 4, Lines 56-67 and Col. 5, Lines 1-65, wherein an FS data structure including FS data is accessed, the FS data containing reliability and failure rate information, i.e. failure mode characterizations, and safety mechanisms, i.e. safety data, on components); and
compiling the safety library components and the hardware IP, including mapping instances in the hardware IP to corresponding safety library components (Nardi Col. 2, Lines 39-43, Col. 7, Lines 1-14, and Col. 10, Lines 2-44, wherein the FS data is mapped to the circuit components), and aggregating the characterizations and safety data of the mapped components (Nardi Col. 6, Lines 28-44 and Col. 11, Lines 18-20, wherein the FS data may be aggregated in a single file).
Regarding Claim 12, Nardi teaches a synthesis tool comprising:
memory (Nardi Col. 24, Lines 4-19, see memory); and
a processing unit (Nardi Col. 23, Lines 48-64, see processors),
wherein the memory stores code that is executed by the processing unit to cause the tool to perform failure mode, effects and diagnostic analysis (FMEDA) (FMEDA) (Nardi Col. 3, Lines 13-15, see design flow using FMEDA) on intellectual property (IP) including:
accessing a safety component library, each component in the library having failure mode characterizations and safety data about a model representation of the IP (Nardi Col. 4, Lines 56-67 and Col. 5, Lines 1-65, wherein an FS data structure including FS data is accessed, the FS data containing reliability and failure rate information, i.e. failure mode characterizations, and safety mechanisms, i.e. safety data, on components); and
compiling the safety library components and the IP, the compiling including: mapping instances in the IP hardware to corresponding safety library components (Nardi Col. 2, Lines 39-43, Col. 7, Lines 1-14, and Col. 10, Lines 2-44, wherein the FS data is mapped to the circuit components); and
aggregating the characterizations and safety data of the mapped components (Nardi Col. 6, Lines 28-44 and Col. 11, Lines 18-20, wherein the FS data may be aggregated in a single file).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC D LEE whose telephone number is (571)270-7098. The examiner can normally be reached Monday-Thursday.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jack Chiang can be reached at 571-272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ERIC D LEE/Primary Examiner, Art Unit 2851