DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 and 6 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0367727 A1) in view of Chiu (US 2022/0319945 A1) as evidenced by Chen ‘030 (US 2023/0040030 A1) and Chen ‘019 (US 2022/0302019 A1).
Regarding claim 1, Chang teaches a semiconductor structure comprising:
a semiconductor chip (¶ [0005], [0016]: FET) with a front side back-end-of-line (BEOL) interconnect wiring (120; see Figs. 30A-C; as evidenced by Chen ‘019 ¶ [0029], high-level interconnects are formed in the BEOL process step); and
a carrier wafer (150) completely covering and directly bonded (¶ [0081]-[0082]: dielectric-to-dielectric bonding is direct bonding as evidenced by Chen ‘030 ¶ [0052]) to the front side BEOL interconnect wiring, wherein:
a front side surface (bottom surface of 150) of the carrier wafer copper is planar.
Chang further teaches the carrier wafer to be made of various materials such as ceramics and silicon (¶ [0080]). However, Chang does not teach: wherein the carrier is made of copper and the copper carrier wafer has a thickness between 200 micrometers (um) and 249 m.
Chiu, in the same field of invention, teaches a device comprising of a copper carrier wafer (30W; ¶ [0069]: carrier wafer 30W may be formed of silicon, copper, etc. ), wherein the copper carrier wafer having a thickness between 200 micrometers (um) and 249 m (¶ [0069]: 100 μm and 300 μm).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Chiu into the device of Chang to substitute the material of the carrier with that of copper and to optimize the range of the thickness of the carrier between 200 to 249 micrometers. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of swapping materials that are used for the same purpose of providing a base platform in the attachment methods in semiconductor devices and for optimizing the thickness of the carrier for the purpose of improving the mechanical rigidity of the device structure (Chiu ¶ [0069]).
Regarding claim 5, the semiconductor structure of claim 1, wherein the semiconductor chip includes a backside BEOL interconnect wiring (136 see Chang Fig. 30A-C; as evidenced by Chen ‘019 ¶ [0029], high-level interconnects are formed in the BEOL process step), under (i) a thinned semiconductor substrate (50; see Chang Fig. 23A and ¶ [0084] describing the thinning process) and (ii) one or more through-silicon vias (130; Fig. 30C) .
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0367727 A1) in view of Chiu (US 2022/0319945 A1) as applied to claim 1 above, and further in view of Hsieh (US 2021/0225916 A1).
Regarding claim 2, Chang et al. teach the semiconductor structure of claim 1 and further teaches directly bonding the copper carrier wafer to the front side BEOL interconnect wiring using dielectric-to-dielectric bonding (Chang ¶ [0081]-[0082]), but do not explicitly teach: wherein the cooling element directly bonded to the front side BEOL interconnect wiring is a hybrid bond.
Hsieh, in the same field of invention, teaches a direct bonding process that can be dielectric-to-dielectric bonding, oxide-to-copper bonding, or hybrid bonding (¶ [0037]). Hence Chang et al. in view of Hsieh teaches the carrier wafer copper cooling element being directly bonded to the front side BEOL interconnect wiring through a hybrid bond.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the dielectric-to-dielectric bonding of Chang with the hybrid bonding of Hsieh for the same purpose of providing direct bonding between the carrier wafer copper cooling element and the front side BEOL interconnect wiring (see Hsieh ¶ [0037] ).
Regarding claim 4, the semiconductor structure of claim 2, wherein the hybrid bond is selected from the group consisting of an oxide hybrid bond and an oxide-copper hybrid bond (Hsieh ¶ [0037]: oxide-to-copper bonding ).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0367727 A1) in view of Poh (US 2013/0154123 A1) and Haba (US 2023/0154828 A1) as evidenced by Chen ‘030 (US 2023/0040030 A1) and Chen ‘019 (US 2022/0302019 A1).
Regarding claim 6, Chang teaches a semiconductor structure comprising:
a semiconductor chip (¶ [0005], [0016]: FET) with a front side back-end-of-line (BEOL) interconnect wiring (120; see Figs. 30A-C; as evidenced by Chen ‘019 ¶ [0029], high-level interconnects are formed in the BEOL process step), a middle-of-line (MOL) layer (112, 114; as evidenced by Chen ‘019 ¶ [0028], intermediate interconnects are formed in the MOL process step), a front-end-of-line (FEOL) device (102, 92, and 95 are the gate, source and drain of the FET; as evidenced by Chen ‘019 ¶ [0027], transistor-level structures are formed in the FEOL process step), a backside BEOL interconnect wiring (136; as evidenced by Chen ‘019 ¶ [0029], high-level interconnects are formed in the BEOL process step), and one or more through-silicon vias (130; see Fig. 30C) passing through a substrate (50; ¶ [0016]: made of silicon) between the FEOL device and the backside BEOL interconnect wiring; and
a carrier wafer (150), completely covering and directly bonded (¶ [0081]-[0082]: dielectric-to-dielectric bonding is direct bonding as evidenced by Chen ‘030 ¶ [0052] ), using an oxide bond (¶ [0081]: 152A & 152B are made of oxides), to the front side BEOL interconnect wiring (see Fig. 30A-C), wherein a front side surface (bottom surface of 150) of the copper carrier wafer element is planar.
Chang further teaches the carrier to be comprised of various materials such as ceramics (¶ [0080]). However, Chang does not teach the carrier to be made of copper.
Poh, in the same field of invention, teaches a carrier to be made of ceramic or copper (¶ [0030]-[0031] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Poh into the device of Chang to substitute the ceramic material of the carrier with that of copper, thereby making the copper carrier to be a cooling element. The ordinary artisan would have been motivated to modify the prior art mentioned above in the manner set forth above for at least the purpose of obtaining the predictable result of using the copper carrier as a cooling element due to the thermal conductive characteristics of copper, for the further purpose of improving the heat dissipation and the performance and reliability of the device (Poh ¶ [0002], [0031]-[0032]).
As mentioned above, Chang further teaches the direct bond to be an oxide bond (¶ [0081]-[0082]). However, Chang in view of Poh does not teach the copper cooling element having a plurality of microchannels and its direct bonding to be using an oxide hybrid bond.
Haba, in the same field of invention, teaches a copper cooling element (1391, Fig. 3A; ¶ [0020]: “the inner bottom wall of the fluidic cooling unit includes 391 formed of a semiconductor material (e.g., Si) or fingers 392 or 393 formed of a metal (e.g., copper)”) with a plurality of microchannels (Fig. 3A shows channels in between fingers 391 & 392 & 393; Haba ¶ [0010] also teaches the device to be a microelectronic device; hence these channels are microchannels) and its direct bonding to be using an oxide hybrid bond (¶ [0031]: “dielectric-to-dielectric hybrid bonds can be formed using the direct bonding techniques”; ¶ [0029]: “dielectric materials for direct bonding include but are not limited to inorganic dielectrics, such as silicon oxide” ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Haba into the device of Chang in view of Poh to add a plurality of microchannels in the copper cooling element and to substitute the oxide bond with that of a hybrid oxide bond. The ordinary artisan would have been motivated to modify the said prior art in the manner set forth above for at least the purpose of using the microchannels created by the finger features inside the cooling element to improve the heat dissipation of the structure (Haba ¶ [0020]), and to substitute any known direct bonding techniques for the same purpose of bonding the metallic carrier to a conductive element of the front side BEOL interconnect (¶ [0020] :” the fluidic cooling unit to the bottom chip may be formed by directly bonding (e.g., direct hybrid bonding, for example, using DBI® processes) a metal feature of the fluidic cooling unit to a conductive via”).
Regarding claim 7, the semiconductor structure of claim 6, wherein the copper carrier wafer, with the plurality of microchannels, includes chilled, circulating water (Haba ¶ [0014]: “the fluid can include a gas or a liquid (e.g., water or dielectric liquid)... the fluid can be cooled, before returning to the cavity”) in the plurality of microchannels.
Regarding claim 8, the semiconductor structure of claim 6, wherein the copper carrier wafer, with the plurality of microchannels, has a similar thermal co-efficient of expansion (Haba ¶ [0012], ¶ [0015]: teaches CTE matching) as the backside BEOL interconnect wiring (also note that Chang ¶ [0078] teaches wiring 122 of front side interconnect layer 120 to be made of copper and that Haba ¶ [0020] teaches cooling element to be made of copper; hence the CTE of the two structures are similar).
Regarding claim 9, the semiconductor structure of claim 8, wherein the copper carrier wafer, with the plurality of microchannels, includes circulating chilled water (Haba ¶ [0014]: “the fluid can include a gas or a liquid (e.g., water or dielectric liquid)... the fluid can be cooled, before returning to the cavity”) in the plurality of microchannels.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Chang (US 2022/0367727 A1) in view of Poh (US 2013/0154123 A1) and Haba (US 2023/0154828 A1), as applied to claim 6 above, and further in view of Hsieh (US 2021/0225916 A1).
Regarding claim 10, Chang et al. teach the semiconductor structure of claim 6 and further teaches directly bonding the carrier wafer copper cooling element to the front side BEOL interconnect wiring using dielectric-to-dielectric bonding (Chang ¶ [0081]-[0082]; Haba ¶ [0031] ) using an oxide hybrid bond (Haba ¶ [0029], [0031]). However, Chang et al. do not teach: wherein the carrier wafer copper cooling element directly bonded to the front side BEOL interconnect wiring uses a direct bond selected from the group consisting of an oxide hybrid bond and an oxide-copper hybrid bond.
Hsieh, in the same field of invention, teaches a direct bonding process that can be dielectric-to-dielectric bonding or oxide-copper hybrid bonding (¶ [0037]). Hence Chang et al. in view of Hsieh teaches the carrier wafer copper cooling element being directly bonded to the front side BEOL interconnect wiring through an oxide-copper hybrid bond.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the hybrid oxide bonding of Chang et al. with the oxide-copper hybrid bonding of Hsieh for the same purpose of providing direct bonding between the carrier wafer copper cooling element and the front side BEOL interconnect wiring (see Hsieh ¶ [0037] ).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/ Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
