DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on March 20, 2026 has been entered.
Response to Arguments
Applicant’s arguments, see Remarks, filed on March 2, 2026, with respect to claims 1 and 6 have been fully considered and are persuasive. The 35 U.S.C. § 112 (b) rejection of claims 1-10 has been withdrawn.
Applicant's arguments filed on March 2, 2026, with respect to 35 U.S.C. § 103 rejections of claim 1 have been fully considered but they are not persuasive. The applicant argues that the prior rejection based on Tsai in view of Dogiamis does not teach “a carrier wafer copper cooling element.” The examiner respectfully disagrees. Paragraphs [0005], [0008], [0034], [0041] of the instant application discloses a carrier wafer made of silicon that is then replaced with various elements such as a copper plate or a copper cooling element with water-filled microchannels. Hence, the examiner finds that the applicant, being his or her own lexicographer, would describe the structure that replaced the silicon carrier wafer to be “a carrier wafer copper cooling element,” with the term not implying any other differentiating structure. In other words, with the claim 1 being a device claim, the examiner finds that the term “carrier wafer copper cooling element” does not present a differentiating structure from what is being taught by Tsai in view of Dogiamis. Furthermore, upon further search and considerations, the examiner finds that the claims can also be taught by Tsai in view of Koller.
The applicant further argues that other references used to reject dependent claims 2, 4-5, and 6-10 do not teach “a carrier wafer copper.” The examiner finds this argument moot due to the reasons above.
In summary, this application is not placed in a condition for an allowance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2022/0359369 A1) in view of Nagai (US 2022/0285245 A1) and Dogiamis (US 2022/0399249 A1).
Regarding claim 1, Tsai teaches a semiconductor structure (see Abstract) comprising:
a semiconductor chip (¶ [0005]: field-effect transistor) with a front side back-end-of-line (BEOL) interconnect wiring (120, see Fig. 29 and ¶ [0009]: front-side BEOL interconnect structure); and
a carrier wafer cooling element (160; the heat sink 160 is structurally the same as “a carrier wafer cooling element,” since the term “carrier wafer” does not imply any differentiating structure; see Response to Arguments above) completely covering (Fig. 29 shows 160 completely covering 120) and directly bonded to the front side BEOL interconnect wiring (¶ [0099]: “the heat sink 160 may be bonded to the front-side interconnect structure 120 through dielectric-to-dielectric bonding, without using any adhesive material… Bonding the heat sink 160 directly to the front-side interconnect structure 120 through fusion bonding may decrease thermal resistance…”, emphasis added).
Tsai further teaches the carrier wafer cooling element to be made of various materials including a metal (¶ [0099]: “the heat sink 160 may comprise materials such as silicon, glass, a metal, a polymer, or the like” ). However, Tsai does not teach the carrier wafer cooling element to be made of copper.
Nagai, in the same field of invention, teaches a carrier wafer cooling element (heat sink plate 31-36 in Fig. 1-3 and ¶ [0031] ; also, heat sink plate 231 in Fig. 7) to be made of various materials (¶ [0025]: metal or graphite ) including copper (¶ [0049] ). Hence, Tsai in view of Nagai teaches the carrier wafer cooling element to be a carrier wafer copper cooling element.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Nagai into the device of Tsai to substitute the generic metal material of the carrier wafer cooling element of Tsai with that of copper for the predictable result of providing a heat exchange away from the semiconductor chip, with the person of ordinary skill noting that substitution can be made of equivalent materials known in the prior art used for the same purpose of providing such heat exchange. See also MPEL § 2143 (I)(B).
However, Tsai does not teach the cooling element, wherein a front side surface of the carrier wafer copper cooling element is planar.
Dogiamis, in the same field of invention, teaches a cooling element (136 & 138; see Fig. 11), wherein a front side surface (top surface of the top portion of 136) of the cooling element is planar (Fig. 11 shows the top surface of the top portion of 136 is flat with no visible ridges).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Dogiamis into the device of Tsai to make the front side surface of the cooling element planar. The ordinary artisan would have been motivated to modify Tsai in the manner set forth above for at least the purpose of providing a cooling mechanism (124, see Dogiamis Fig. 11) for a package that consists of the semiconductor chip (134, this is analogous to the semiconductor chip of Tsai, as 134 is directly bonded to the cooling element 136 & 138; see ¶ [0056]), another semiconductor chip (132), and a package substrate (120), wherein the two semiconductor chips are vertically stacked with the cooling element (as shown in Fig. 11), and wherein the cooling mechanism acts as a sealed enclosure for a cooling liquid (Dogiamis ¶ [0054]), for the further purpose of integrating multiple semiconductor chips in a multi-chip package for increased device density (Dogiamis ¶ [0003]-¶ [0004]).
Regarding claim 26, the semiconductor structure of claim 1, wherein the carrier wafer copper cooling element has a thickness between 200 micrometers (µm) and 800 µm (see Dogiamis ¶ [0067] and Fig. 25: channel widths and heights in the range of 50-1000 µm).
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2022/0359369 A1) in view of Koller (DE 10 2010 000518 A1; see NPL for English translation).
Regarding claim 1, Tsai teaches a semiconductor structure (see Abstract) comprising:
a semiconductor chip (¶ [0005]: field-effect transistor) with a front side back-end-of-line (BEOL) interconnect wiring (120, see Fig. 29 and ¶ 0009: front-side BEOL interconnect structure); and
a cooling element (160) completely covering (Fig. 29 shows 160 completely covering 120) and directly bonded to the front side BEOL interconnect wiring (¶ [0099]: “the heat sink 160 may be bonded to the front-side interconnect structure 120 through dielectric-to-dielectric bonding, without using any adhesive material… Bonding the heat sink 160 directly to the front-side interconnect structure 120 through fusion bonding may decrease thermal resistance…”, emphasis added).
Tsai further teaches the cooling element to be made of various materials including a metal (¶ [0099]: “the heat sink 160 may comprise materials such as silicon, glass, a metal, a polymer, or the like” ). However, Tsai does not explicitly teach the cooling element to be a planar carrier wafer that is made of copper.
Koller, in the same field of invention, teaches a planar cooling element (32; see Figs. 2 and 3; ¶ [0036] of English Translation: “the support substrate 32 is provided as a copper layer, so that the subsequent processing transforms the semiconductor substrate 30 into an ultra-thin semiconductor power chip which has a copper heat sink”; ¶ [0045] “the support substrate 32 is provided as a heat sink for the TSL 36” ) that is a carrier wafer (32 is a carrier substrate, see ¶ [0041]: 32 is a carrier substrate; substrates are known in the art to be provided as a wafer, see ¶ [0034] ) made of copper (¶ [0036] ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Koller into the device of Tsai to substitute the cooling element of Tsai with a planar carrier wafer copper cooling element. The ordinary artisan would have been motivated to modify Tsai in the manner set forth above for at least the purpose of improving the dimensions of the device of Tsai into an ultra-thin semiconductor device for various applications such as mobile phones (Koller ¶ [0002] of the English translation; ¶ [0028]: carrier wafer 32 is used as a support substrate to thin the semiconductor device ) and for substituting the unknown material of the cooling element of Tsai with equivalent materials such as copper, which is known in the art to be used for the same purpose of providing heat dissipation (¶ [0036] ).
Regarding claim 26, the semiconductor structure of claim 1, wherein the carrier wafer copper cooling element has a thickness between 200 micrometers (µm) and 800 µm (see Koller ¶ [0036]: 250-750 micrometers).
Claims 2 and 4 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2022/0359369 A1) in view of Koller (DE 10 2010 000518 A1) as applied to claim 1 above, and further in view of Hsieh (US 2021/0225916 A1).
Regarding claim 2, Tsai et al. teach the semiconductor structure of claim 1 and further teaches directly bonding the carrier wafer copper cooling element to the front side BEOL interconnect wiring using dielectric-to-dielectric bonding (Tsai ¶ [0099] ), but do not explicitly teach: wherein the cooling element directly bonded to the front side BEOL interconnect wiring is a hybrid bond.
Hsieh, in the same field of invention, teaches a direct bonding process that can be dielectric-to-dielectric bonding, oxide-to-copper bonding, or hybrid bonding (¶ [0037]). Hence Tsai et al. in view of Hsieh teaches the carrier wafer copper cooling element being directly bonded to the front side BEOL interconnect wiring through a hybrid bond.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the dielectric-to-dielectric bonding of Tsai with the hybrid bonding of Hsieh for the same purpose of providing direct bonding between the carrier wafer copper cooling element and the front side BEOL interconnect wiring (see Hsieh ¶ [0037] ).
Regarding claim 4, Tsai et al. teach the semiconductor structure of claim 2, wherein the hybrid bond is selected from the group consisting of an oxide hybrid bond and an oxide-copper hybrid bond (Hsieh ¶ [0037]: oxide-to-copper bonding ).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2022/0359369 A1) in view of Koller (DE 10 2010 000518 A1) as applied to claim 1 above, and further in view of Wu (US 2023/0402367 A1) as evidenced by Greene (US 2019/0006506 A1).
Regarding claim 5, Tsai et al. teach the semiconductor structure of claim 1, wherein the semiconductor chip includes a backside BEOL interconnect wiring (140: Fig. 27A shows 140 formed after device layer 109 is formed; as evidenced by Greene ¶ [0043], such wiring formed after the device layer is a back-end-of-line (BEOL) interconnect wiring) under (i) a thinned semiconductor substrate (50; see Fig. 23A and ¶ [0084] describing the thinning process).
Tsai further teaches a device layer (109, see Fig. 22C) in the thinned substrate (50).
However, Tsai et al. do not teach: (ii) one or more through-silicon vias.
Wu, in the same field of invention, teaches a semiconductor structure (Fig. 1A, ¶ [0019]) of a semiconductor chip (¶ [0002]) having a frontside BEOL interconnect wiring (116&101&113; ¶ [0002]), a device layer (106 & 107 & 108 & 109 & 110 ), and a backside BEOL interconnect wiring (119; ¶ [0003]),
wherein the semiconductor chip further includes one or more through-silicon vias (102; note: Tsai ¶ [0016] teaches substrate 50 of device layer 109 to be made of silicon; hence Tsai et al. in view of Wu teaches 102 to be a via that goes through silicon, i.e., a through-silicon via ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Tsai et al. to add a one or more through-silicon vias in a semiconductor structure of a semiconductor chip at least comprising of a backside BEOL interconnect wiring, a thinned semiconductor substrate, and a frontside BEOL interconnect wiring. The ordinary artisan would have been motivated to modify Tsai et al. in the manner set forth above for at least the purpose of using the through-silicon via as part of a conductive pathway for a first reference voltage (VDD, see Wu ¶ [0025]) to conduct from the backside BEOL interconnect wiring to one of the devices (108, see Wu Fig. 1B) in the device layer of the semiconductor substrate (106), while providing a separate conductive pathway for a second reference voltage (VSS, see Wu ¶ [0026]).
Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2022/0359369 A1) in view of Wu (US 2023/0402367 A1), Haba (US 2023/0154828 A1), and Koller (DE 10 2010 000518 A1; see NPL for English translation) as evidenced by Greene (US 2019/0006506 A1).
Regarding claim 6, Tsai teaches a semiconductor structure (abstract) comprising:
a semiconductor chip (¶ [0005]: field-effect transistor) with a front side back-end-of-line (BEOL) interconnect wiring (120, see Fig. 29 and ¶ [0009]: front-side BEOL interconnect structure), a backside BEOL interconnect wiring (140: Fig. 21A shows 140 formed after device layer 109 is formed; as evidenced by Greene ¶ [0043], such wiring formed after the device layer is a back-end-of-line (BEOL) interconnect wiring);
a cooling element (160; see Tsai Fig. 29) completely covering (Fig. 29 shows 160 completely covering 120) and directly bonded to the front side BEOL interconnect wiring (Tsai ¶ [0099]: “the heat sink 160 may be bonded to the front-side interconnect structure 120 through dielectric-to-dielectric bonding, without using any adhesive material… Bonding the heat sink 160 directly to the front-side interconnect structure 120 through fusion bonding may decrease thermal resistance…”, emphasis added) and that the cooling element is made of metal (Tsai ¶ [0099]).
Tsai further teaches a device layer (109, see Fig. 22C) in a substrate (50). However, Tsai does not teach: one or more through-silicon vias.
Wu, in the same field of invention, teaches a semiconductor structure (Fig. 1A, ¶ [0019]) of a semiconductor chip (¶ [0002]) having a frontside BEOL interconnect wiring (116&101&113; ¶ [0002]), a device layer (106 & 107 & 108 & 109 & 110 ), and a backside BEOL interconnect wiring (119; ¶ [0003]),
wherein the semiconductor chip further includes one or more through-silicon vias (102; note: Tsai ¶ [0016] teaches substrate 50 of device layer 109 to be made of silicon; hence Tsai in view of Wu teaches 102 to be a via that goes through silicon, i.e., a through-silicon via ).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Wu into the device of Tsai to add a one or more through-silicon vias in a semiconductor structure at least comprising of a semiconductor chip having a front side BEOL interconnect wiring and a backside BEOL interconnect wiring. The ordinary artisan would have been motivated to modify Wu in the manner set forth above for at least the purpose of using the through-silicon via as part of a conductive pathway for a first reference voltage (VDD; see Wu ¶ [0025]) to conduct from the backside BEOL interconnect wiring to one of the devices (108; Wu Fig. 1B) in a device layer of the a semiconductor substrate (106), while providing a separate conductive pathway for a second reference voltage (VSS; see Wu ¶ [0026]).
As discussed above, Tsai in view of Wu teaches a cooling element. However, Tsai in view of Wu does not teach: the cooling element is comprised of copper with a plurality of microchannels.
Haba, in the same field of invention, teaches a cooling element (1391, Fig. 3A) is comprised of copper (¶ [0020]: “the inner bottom wall of the fluidic cooling unit includes 391 formed of a semiconductor material (e.g., Si) or fingers 392 or 393 formed of a metal (e.g., copper)”) with a plurality of microchannels (Fig. 3A shows channels in between fingers 391 & 392 & 393; Haba ¶ [0010] also teaches the device to be a microelectronic device; hence these channels are microchannels).
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Haba into the device of Tsai in view of Wu to use copper as the composition of the cooling element and to add a plurality of microchannels in the cooling element in a semiconductor structure at least comprising of a semiconductor chip with a front side BEOL interconnect wiring, a backside BEOL interconnect wiring, one or more through-silicon vias; and the copper cooling element that is directly bonded to the front side BEOL interconnect wiring. The ordinary artisan would have been motivated to modify Tsai in view of Wu in the manner set forth above for at least the purpose of using the microchannels created by the finger features inside the cooling element to increase the heat dissipation of the structure (Haba ¶ [0020]), to substitute an unspecified metallic element that comprises the cooling structure of Tsai (see Tsai ¶ [0099]) with copper, which is known in the art to provide good thermal conductivity, and for the further purpose of matching the CTE of an element directly attached to the cooling structure (Haba ¶ [0015]) in order to reduce cracks in between the bonding surfaces of the cooling structure and the frontside BEOL interconnect wiring (Haba ¶ [0012]).
However, Tsai in view of Wu and Haba does not teach the copper cooling element, to be a carrier wafer having a front side surface that is planar.
Koller, in the same field of invention, teaches cooling element (32; see Figs 2 and 3; ¶ [0036]: “the support substrate 32 is provided as a copper layer, so that the subsequent processing transforms the semiconductor substrate 30 into an ultra-thin semiconductor power chip which has a copper heat sink”; ¶ [0045] “the support substrate 32 is provided as a heat sink for the TSL 36” ) to be a carrier wafer (32 is a carrier substrate, see ¶ [0041]; substrates are known in the art to be provided as a wafer, see ¶ [0034] ) having a front side surface (top surface) that is planar.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to combine the teachings of Koller into the device of Tsai in view of Wu and Haba to substitute the copper cooling element of Tsai in view of Wu and Haba with a planar carrier wafer copper cooling element. The ordinary artisan would have been motivated to modify Tsai in the manner set forth above for at least the purpose of improving the dimensions of the device of Tsai into an ultra-thin semiconductor device for various applications such as mobile phones (Koller ¶ [0002] of the English translation; ¶ [0028]: carrier wafer 32 is used as a support substrate to thin the semiconductor device ).
Regarding claim 7, the semiconductor structure of claim 6, wherein the carrier wafer copper cooling element with the plurality of microchannels includes chilled, circulating water (Haba ¶ [0014]: “the fluid can include a gas or a liquid (e.g., water or dielectric liquid)... the fluid can be cooled, before returning to the cavity”) in the plurality of microchannels.
Regarding claim 8, the semiconductor structure of claim 6, wherein the carrier wafer copper cooling element with the plurality of microchannels has a similar thermal co-efficient of expansion (Haba ¶ [0012], ¶ [0015]) as the backside BEOL interconnect wiring (also note that Tsai ¶ [0078] teaches wiring 122 of front side interconnect layer 120 to be made of copper and that Haba ¶ [0020] teaches cooling element to be made of copper; hence the CTE of the two structures are similar).
Regarding claim 9, the semiconductor structure of claim 8, wherein the carrier wafer copper cooling element with the plurality of microchannels includes circulating chilled water (Haba ¶ [0014]: “the fluid can include a gas or a liquid (e.g., water or dielectric liquid)... the fluid can be cooled, before returning to the cavity”) in the plurality of microchannels.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 2022/0359369 A1) in view of Wu (US 2023/0402367 A1), Haba (US 2023/0154828 A1), and Koller (DE 10 2010 000518 A1; see NPL for English translation), as applied to claim 6 above, and further in view of Hsieh (US 2021/0225916 A1).
Regarding claim 10, Tsai et al. teach the semiconductor structure of claim 6 and further teaches directly bonding the carrier wafer copper cooling element to the front side BEOL interconnect wiring using dielectric-to-dielectric bonding (Tsai ¶ [0099] ). However, Tsai et al. do not teach: wherein the carrier wafer copper cooling element directly bonded to the front side BEOL interconnect wiring uses a direct bond selected from the group consisting of an oxide hybrid bond and an oxide-copper hybrid bond.
Hsieh, in the same field of invention, teaches a direct bonding process that can be dielectric-to-dielectric bonding or oxide-copper hybrid bonding (¶ [0037]). Hence Tsai et al. in view of Hsieh teaches the carrier wafer copper cooling element being directly bonded to the front side BEOL interconnect wiring through an oxide-copper hybrid bond.
A person of ordinary skill in the art, prior to the effective date of the claimed invention, will find it obvious to substitute the dielectric-to-dielectric bonding of Tsai with the oxide-copper hybrid bonding of Hsieh for the same purpose of providing direct bonding between the carrier wafer copper cooling element and the front side BEOL interconnect wiring (see Hsieh ¶ [0037] ).
Conclusion
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS YAP whose telephone number is (703)756-1946. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM ET.
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/DOUGLAS YAP/Assistant Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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