Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “contact area between the first vertical connection wire and the second bonding pad of the second redistribution structure is greater than a contact area between the first vertical connection wire and the first bonding pad of the first redistribution structure” as well as “contact area between the first second connection wire and the fourth bonding pad of the second semiconductor chip is greater than a contact area between the second vertical connection wire and the third bonding pad of the first redistribution structure” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, and 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (US Pat. Pub. 2016/0049385).
Regarding claim 1, Yu teaches a semiconductor package comprising:
a first redistribution structure comprising a first redistribution pattern and a first redistribution insulating layer [fig. 2m, 122 with pattern 122r and insulating layer 122d];
a first semiconductor chip on the first redistribution structure, the first semiconductor chip comprising a first semiconductor substrate [fig. 2m, 116];
a second semiconductor chip on the first semiconductor chip, the second semiconductor chip comprising a central portion vertically overlapping the first semiconductor chip and an outer portion horizontally offset from a sidewall of the first semiconductor chip [fig. 2m, 110 is wider than 116, a central portion of 110 is overlapping 110 and an outer portion is horizontally offset from a sidewall of 116];
an inter-chip connection bump between the first semiconductor chip and the second semiconductor chip [fig. 2m ,118];
a molding layer in contact with the first redistribution structure, the first semiconductor chip, the second semiconductor chip, and the inter-chip connection bump [fig. 2m, 108];
a second redistribution structure on the second semiconductor chip and the molding layer, the second redistribution structure comprising a second redistribution pattern and a second redistribution insulating layer [fig. 2m, 124 comprising pattern 124r and insulating layer 124d];
a first vertical connection wire extending through the molding layer and extending from the first redistribution structure to the second redistribution structure [fig. 2m, 130]; and
a second vertical connection wire extending through the molding layer and extending from the first redistribution structure to the outer portion of the second semiconductor chip [fig. 2m, 112].
The embodiment of Yu shown in fig. 2m fails to teach a first through electrode extending through the first semiconductor substrate of the first semiconductor chip. However, a different embodiment of Yu shown in fig. 1j demonstrates a chip stack between first and second redistribution layers where the first chip has a first through electrode extending through the first substrate of the first chip [fig.1j, first chip 116, through electrode 152, second chip 110, first redistribution 122, second redistribution 124].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of another embodiment of Yu into the method of embodiment of Yu in fig. 2m by forming a first through electrode extending through the first semiconductor substrate. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of providing an extra or additional thermal dissipation path and or power or ground vias [Yu, paragraph [0063]].
Regarding claim 2, Yu discloses the semiconductor package of claim 1, wherein the first semiconductor chip has a first horizontal width in a first horizontal direction, the second semiconductor chip has a second horizontal width in the first horizontal direction that is greater than the first horizontal width of the first semiconductor chip, and each of the first redistribution structure and the second redistribution structure has a third horizontal width that is greater than the second horizontal width of the second semiconductor chip [fig. 2m, the first chip 116 has a first width, the second chip 110 has a second width that is greater than the first width and 122 and 124 have a third width greater than the second width].
Regarding claim 11, Yu teaches the semiconductor package of claim 1, further comprising an upper semiconductor device on the second redistribution structure [fig. 1j, 104].
Regarding claim 12, Yu discloses the semiconductor package of claim 11, wherein at least one of the first semiconductor chip and the second semiconductor chip comprises a logic chip [paragraph [0025]] and the upper semiconductor device comprises a memory chip [paragraph [0042]].
Regarding claim 13, Yu fails to specifically teach the first and second vertical connection wires comprise copper, gold or silver. However, other through via connections disclosed in Yu teach the user copper [paragraph [0060]], it would be well known in the art to utilize the same material for a similarly designed interconnect structure.
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of what is well known into the method of Yu by using copper to form the first and second vertical connections. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of utilizing known interconnect/via materials to ensure successful device fabrication.
Claim(s) 3 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yu as applied to claims 1, 2, and 11-13 above, and further in view of Kuo et al. (US Pat. Pub. 2021/0375708).
Regarding claim 3, Yu teaches a first vertical connection wire comprises a first end portion connected to a first bonding pad of the first redistribution structure and a second end portion connected to a second bonding pad of the second redistribution structure [paragraph [0037] teaches 130 is electrically coupled to RDLs 122 and 124 via layers 120 and 128, a bonding pad would be required and present to facilitate the electrically coupling].
Yu fails to teach different contact area sizes between the vertical connection wire and the first and second bond pads. However, Kuo teaches vertical connection wires that are tapered which would yield a contact area which is greater between a second redistribution bond pad and the wire versus a contact area and a first redistribution bond pad [fig. 5f. tapered vertical connection wire 116t between upper redistribution 144 and lower redistribution 144’].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Kuo into the method of Yu by having tapered vertical connection wires yielding a contact area between the first vertical connection wire and the second bonding pad of the second redistribution structure being greater than a contact area between the first vertical connection wire and the first bonding pad of the first redistribution structure. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of preventing bubble formation during processing such as forming the molding compound [Kuo, paragraph [0034]].
Regarding claim 4, Yu teaches a second vertical connection wire comprises a first end portion connected to a third bonding pad of the first redistribution structure and a second end portion connected to a fourth bonding pad of the second semiconductor chip [paragraph [0021] teaches 112 is electrically coupled to RDL 122 and chip 110 via layers 120 and bond pads 110c, a bond pad would be present in layer 120 to facilitate the electrical coupling].
Yu fails to teach different contact area sizes between the vertical connection wire and the first and second bond pads. However, Kuo teaches vertical connection wires that are tapered which would yield a contact area which is greater between a second redistribution bond pad and the wire versus a contact area and a first redistribution bond pad [fig. 5f. tapered vertical connection wire 116t between upper redistribution 144 and lower redistribution 144’].
It would have been obvious to one of ordinary skill in the art at the time of the invention to incorporate the teachings of Kuo into the method of Yu by having tapered vertical connection wires yielding a contact area between the second vertical connection wire and the fourth bonding pad of the second semiconductor chip being greater than a contact area between the second vertical connection wire and the first third pad of the first redistribution structure. The ordinary artisan would have been motivated to modify Yu in the manner set forth above for at least the purpose of preventing bubble formation during processing such as forming the molding compound [Kuo, paragraph [0034]].
Allowable Subject Matter
Claims 15-20 are allowed.
Claims 5-10 and 14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 15, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a first conductive connection pillar extending between a first lower connection pad of the first semiconductor chip and a first redistribution pad of the first redistribution structure in combination with a first semiconductor chip comprising a first semiconductor substrate an a first through-hole extending through the first semiconductor substrate.
Regarding claim 19, the prior art fails to disclose or suggest the device as claimed. Specifically, the prior art fails to teach a first conductive connection pillar between the first semiconductor chip and the first redistribution structure and comprising copper along with a molding layer in contact with the first redistribution structure, the first semiconductor chip, the second semiconductor chip, the first conductive connecting pillar, the second conductive connection pillar and the inter-chip connection bump.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M PARKER whose telephone number is (571)272-8794. The examiner can normally be reached M-F 7:30am - 3:30pm.
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/JOHN M PARKER/Examiner, Art Unit 2899