DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions Applicant’s election without traverse of Group I and cla i ms 1-12 in the reply filed on 2/9/2026 is acknowledged. Claim s 13-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Groups II and III, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/9/2026. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1 , 5 and 10-12 are rejected under 35 U.S.C. 103 as being unpatentable over Ou et al. ( US 2023 / 0127051 A1 ) , and further in view of Tolchinsky et al. ( US 2005 / 0070048 A1 ), Malhi et al. ( US 5349207 A ) and Matsumae et al. (J. Appl. Phys. 130, 085303, 2021) . Re Claim 1, Ou teaches a method of making a composite substrate (Figs. 1-5) , the method comprising: bonding the silicon carbide wafer (200, Figs. 3-5, para [0056]) with a gallium oxide wafer (100, Figs. 3-5, para [0054]) ; thinning the bonded gallium oxide wafer (thinning of gallium oxide layer 100 to a thinned layer 110, Fig. 5, para [0060]) to a thickness of about 2 to about 25 microns ( thickness of the gallium oxide layer 110 is in the order of microns , para [0060] ) . Ou also does not disclose the following: depositing a silicon layer on a surface of a silicon carbide wafer; smoothing the deposited silicon layer by Chemical Mechanical Polishing (CMP) and first annealing to produce a flat silicon surface on the silicon carbide wafer; second annealing the bonded silicon carbide wafer and gallium oxide wafer; In a related semiconductor art, Tolchinsky teaches a method of improving the surface roughness of SiC substrate before it is being attached to another semiconductor substrate, since SiC is a very hard material that may be difficult to planarize to a perfectly smooth surface (para [0029]). Tolchinsky teaches a SiC layer 220 (Fig. 2b), whose rough surface can be improved by depositing a transition layer 250 (like polysilicon) followed by planarizing and polishing to create a smooth surface (para [0029]), on which another semiconductor layer 210 can be attached. Though Tolchinsky does not explicitly disclose how the planarization or polishing is done , however, with respect to another embodiment, Tolchinsky disclosed that t he planarization and polishing can be done by c hemical m echanical p olishing (para [0032]). Additionally, Malhi teaches that an annealing step can be performed to increase the bond strength between the silicon layer and the SiC substrate (Col.4 lines 3-6). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to deposit a silicon layer on the surface of SiC substrate of Ou followed by a planarization and polishing step as taught by Tolchinsky as that would improve the smoothness of the SiC substrate and help in better adhesion to the gallium oxide semiconductor layer (para [0029], Tolchinsky ). Additionally, an annealing step can be performed to the Si/ SiC composite substrate, before bonding to the gallium oxide layer as taught by Malhi , as that would increase the bond strength between the silicon layer and the SiC substrate (Col.4 lines 3-6, Mahi ). Ou modified by Tolchinsky and Mahi does not disclose: second annealing the bonded silicon carbide wafer and gallium oxide wafer; Related art, Matsumae teaches and annealing step to the bonded SiC /Ga 2 O 3 composite substrate as that would be improve the bond ing strength of the composite layer (Pg 085303-2, left-hand col., lines 11-15 of para [4]). It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, absent unexpected results, to modify the method Ou modified by Tolchinsky and Mahi such that to include a second annealing step to the bonded silicon carbide wafer and the gallium oxide wafer, as taught by Matsumae , as that would improve the bonding strength of the composite layer. Re Claim 5 , Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 1, wherein the first annealing includes annealing in an oxygen free environment at a temperature in a range of about 1100°C to about 1400°C for about 10 minutes or longer (first annealing of Si/ SiC composite is done in a nitrogen ambient at approximately 1100°C for 30 minutes , Col.4 lines 3-6, Mahi ) . Re Claim 10 , Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 1, wherein the deposited silicon layer is about 5 to about 50 nm in thickness (transitional silicon layer 250 can be between 10 nm and 100 nm, para [0029], Tolchinsky ) . Re Claim 1 1 , Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 1, wherein the gallium oxide is β-Ga 2 O 3 (layer 100 can β-Ga 2 O 3 single crystal wafer , para [0054], Ou ) . Re Claim 1 2 , Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 1, wherein Matsumae teaches that the second annealing includes heating the bonded silicon carbide wafer and gallium oxide wafer to a temperature of about 250 °C (Pg 085303-2, left-hand col., lines 11-15 of para [4]) and does not explicitly disclose an annealing temperature of 300 °C to about 450°C. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the annealing temperature depending on the experimental conditions, surface morphologies and sample qualities, and arrive at the claimed value . With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller , 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). Claim s 2 -3 are rejected under 35 U.S.C. 103 as being unpatentable over Ou et al. ( US 2023 / 0127051 A1 ) , Tolchinsky et al. ( US 2005 / 0070048 A1 ), Malhi et al. ( US 5349207 A ) and Matsumae et al. (J. Appl. Phys. 130, 085303, 2021) as applied in claim 1 above, and further in view of and further in view of Lei et al. ( US 2016 / 0315009 A1 ) and Xie et al. ( US 2006 / 0255425 A1 ) . Re Claim 2, Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 1, but does not disclose dividing the gallium oxide layer into islands with a size of about 2 centimeters. However, in a related art, Lei teaches (Figs. 5E-5H) how to divide a semiconductor wafer (500’) into individual islands of dies (514), which will later form integrated chips. Additionally, Xie teaches that conventional chip size is 1 cm × 1 cm (para [0043], Xie) , which is the size of individual dies. It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to divide the gallium oxide layer of Ou modified by Tolchinsky , Mahi and Matsumae , and form individual dies as taught by Lei , which will be further processed to form integrated chips. T he selection of a known process based on its suitability for its intended use of dividing a wafer into individual dies, supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07. Additionally, Xie teaches that conventional chip size is 1 cm × 1 cm, which is the size of individual islands of dies. It would have been obvious to one of ordinary skill in the art, at the time of invention, to optimize the size of the individual dies depending on the needs and functionalities of the devices to be formed and arrive at the claimed value . With respect to the limitations of the claim, where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. See In re Aller , 220 F.2d 454, 456, 105 USPQ 233 (CCPA 1955). Re Claim 3 , Ou modified by Tolchinsky , Mahi , Matsumae , Lei and Xie teaches t he method of claim 2, wherein dividing the gallium oxide layer into islands comprises: placing a lithography mask and photoresist (504, Fig. 5E, para [0053] , Lei ) on the bonded gallium oxide wafer (wafer 500’, Fig. 5E, para [0052] , Lei ) ; exposing the lithography mask and photoresist to light (laser ablation, Fig. 5F, para [0053] , Lei ) to etch the photoresist into etched photoresist islands (patterned mask 512, Fig. 5F , Lei ) and expose windows of the gallium oxide layer (exposed windows of wafer 500’, Fig. 5F , Lei ) ; etching the exposed windows of the gallium oxide layer to generate the gallium oxide islands (see Fig. 5G , Lei ) ; and stripping the lithography mask and etched photoresist islands from the gallium oxide islands (see Fig. 5H, para [0057] , Lei ) . Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Ou et al. ( US 2023 / 0127051 A1 ) , Tolchinsky et al. ( US 2005 / 0070048 A1 ), Malhi et al. ( US 5349207 A ) and Matsumae et al. (J. Appl. Phys. 130, 085303, 2021) as applied in claim 1 above, and further in view of and further in view of Chen et al. ( US 2007 / 0052080 A1 ) Re Claim 4, Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 1, wherein the thinning of the gallium oxide wafer includes grinding or wet etching, and CMP (see paras [0060] – [0062] , Ou ), but does not explicitly state that the thinning step includes all three processes . In a related semiconductor art, Chen teaches that t he wafer thinning process can be implemented by for example grinding, polishing, CMP, isotropic wet etching or plasma etching, or any combinations of the above processes (paras [0014] – [0015]) . It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the thinning step of the gallium oxide layer of Ou modified by Tolchinsky , Mahi and Matsumae , by either grinding, polishing, CMP, isotropic wet etching or plasma etching, or any combinations of the above processes as taught by Chen (paras [0014] – [0015]) . T he selection of a known process based on its suitability for its intended use of thinning a wafer, supports a prima facie obviousness determination as established in Sinclair & Carroll Co. v. Interchemical Corp. , 325 U.S. 327, 65 USPQ 297 (1945), see MPEP 2144.07. Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Ou et al. ( US 2023 / 0127051 A1 ) , Tolchinsky et al. ( US 2005 / 0070048 A1 ), Malhi et al. ( US 5349207 A ) and Matsumae et al. (J. Appl. Phys. 130, 085303, 2021) as applied in claim 5 above, and further in view of and further in view of Ito et al. ( US 2002 / 0061660 A1 ). Re Claim 6, Ou modified by Tolchinsky , Mahi and Matsumae teaches t he method of claim 5, wherein the first annealing includes annealing the silicon layer on the surface of the silicon carbide wafer performed in a nitrogen atmosphere (see claim 5 above) and does not disclose that the annealing is performed in a hydrogen or argon environment. In a related semiconductor art, Ito teaches that t he atmosphere used for annealing can include at least one gas selected from rare gases such as helium, neon, and argon, inert gases such as nitrogen, and hydrogen gas , which s uppress growth of defects by an oxygen impurity (para [0035]) . It would have been prima facie obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to substitute the inert nitrogen atmosphere during the first annealing of Ou modified by Tolchinsky , Mahi and Matsumae , by another inert hydrogen atmosphere, as taught by Ito (paras [0035]), as both s uppress growth of defects by an oxygen impurity . The substitution of a known material for its known purpose to yield predictable results is prima facie obvious. Also see KSR Int'l Co. v. Teleflex Inc. , 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Allowable Subject Matter Claim s 7-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claim 7 recites the limitation wherein, the method of claim 1 further comprises, “ depositing a wetting agent prior to depositing the silicon layer on the surface of the silicon carbide wafer ”. In the Examiner’s opinion, this limitation is neither anticipated nor made obvious by the prior art of record, when viewed in the context of the independent claim 1, as a whole. Claims 8-9 depend from claim 7 and are allowable for at least the reasons above. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. 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