DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on June 2, 2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 17, 2023, April 4, 2024 is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Vertical Memory Device With Decreased Device Defects
Election/Restrictions
Applicant’s election without traverse of Group III in the reply filed on September 30, 2025 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, 10-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang (US 2020/0027893). Claim 1, Yang discloses (Figs. 3B and 6) a memory device comprising: a substrate (50, lower substrate, Para [0044]) including a cell area (A1, first region, Para [0052]) a cell wiring area (second A2 without area around 194a, Para [0052], hereinafter “cwa”) and a through-hole wiring area (area around connection word line 194a, Para [0091], hereinafter “twa”) ; word line patterns (170, gate horizontal patterns, Para [0051]) on the cell area and the cell wiring area (170 is on A1 and cwa), the word line patterns stacked on the substrate (170s are stacked on 50) and spaced from each other in (170 spaced apart from each other in Z direction) a vertical direction (Z direction), the vertical direction being perpendicular to an upper surface of the substrate (Z direction is perpendicular to upper surface of 50), and the word line patterns extending to the cell wiring area in a direction parallel to the upper surface of the substrate (170 extends to cwa in X direction which is parallel to upper surface of 50); a channel structure (146c, vertical channel structures, Para [0071]) on the cell area (146c is on A1), the channel structure extending in the vertical direction (146c extends in Z direction); first contact plugs (189, gate contact plugs, Para [0090]) on the cell wiring area (189 is on cwa), the first contact plugs extending in the vertical direction (189 extend in Z direction), each of the first contact plugs being electrically connected with a corresponding one of the word line patterns and insulated from remaining word line patterns other than the corresponding one of the word line patterns (each individual 189 is only connected to a corresponding 170 and thus is insulated from remaining 170s); and second contact plugs (180 of 183a, conductive pillar, Para [0075] multiple shown in Fig. 6, hereinafter “plug2”) on the through-hole wiring area (plug2 is on twa), the second contact plugs extending in the vertical direction (plug2 extends in Z direction), wherein at least one of the second contact plugs (plug2) is electrically connected with a part of the word line patterns (plug2 is connected to 194a through 192a which is then connected to word line connection wire 193w, Para [0090] – [0093]).
Claim 3, Yang discloses (Figs. 3B and 6) the memory device of claim 1, wherein the word line patterns (170) include 2n or 2n+1 word line patterns (in fig. 3B there are 10 170s which would be n=5) stacked in the vertical direction on the upper surface of the substrate (170s are stacked in Z direction on upper surface of 50), a first word line pattern (170U, string selection line, Para [0063]) is an uppermost one of the word line patterns (170U is uppermost of 170), n is a positive integer (5 is positive integer), and the part of the word line patterns (170) electrically connected with the at least one of the second contact plugs (170U is connected to 193s which may be connected to plug2 through 194a, Para [0093]) is selected among the first word line pattern of the word line patterns to an n-th word line pattern of the word line patterns from an upper side of the word line patterns (170U is a string selection line which would be selected from 170s). Claim 4, Yang discloses (Figs. 3B and 6) the memory device of claim 1, wherein the word line patterns (170) include a string selection line (170U may be string selection line, Para [0063]) and a word line (170M1/170M2 may be word lines, Para [0065]). Claim 5, Yang discloses (Figs. 3B and 6) the memory device of claim 4, wherein the word line (170M1/170M2) is connected with one of the first contact plugs (170M1/170M2 are connected to 189), and the string selection line (170U) is connected with one of the second contact plugs (170U is connected to 193s which is connected to plug2 through 194a, Para [0093]). Claim 6, Yang discloses (Figs. 3B and 6) the memory device of claim 1, the memory device of claim 1, wherein the word line patterns (170) include a plurality of word lines (170M1/170M2 may be word lines, Para [0065]) and a string selection line (170U may be string selection line, Para [0063]), the string selection is connected with one of the second contact plugs (170U is connected to 193s which is connected to plug2 through 194a, Para [0093]), some of the plurality of word lines are connected with the first contact plugs (some of 170M1/170M2 is connected with 189, for example lowermost 170M1, hereinafter “wp1”) and others of the plurality of word lines are connected with the second contact plugs (others of 170M1/170M2 are connected to 193w which is connected to 194a and plug2, for example middle 170M1, hereinafter “wp2”). Claim 7, Yang discloses (Figs. 3B and 6) the memory device of claim 6, wherein the others of the word lines (wp2) connected with the second contact plugs are above the some of the word lines connected with the first contact plugs (wp2 is above wp1). Claim 10, Yang discloses (Figs. 3B and 6) the memory device of claim 1, further comprising: pad patterns (P, pad region, Para [0092]) on the cell wiring area (P is on cwa) and electrically connected with the word line patterns (P is connected to 170, Para [0092]). Claim 11, Yang discloses (Figs. 3B and 6) the memory device of claim 10, wherein the pad patterns (P) and word line patterns (170) provide a plurality of conductive layers (P and 170 are conductive), the plurality of conductive layers (P/170) each include one of the pad patterns (one of P) and one of the word line patterns (one of 170), each of the first contact plugs (189) is electrically connected with a corresponding one of the pad patterns (each 189 is connected to a corresponding one of P, hereinafter “pad1”) and insulated from remaining pad patterns other than the corresponding one of the pad patterns (189 is only connected to pad1 and insulated from rest of P), such that each corresponding first contact plug among the first contact plugs is electrically connected with the corresponding one of the pad patterns and the corresponding one of the word line patterns in a corresponding conductive layer among the plurality of conductive layers (each 189 is connected with a corresponding P and 170). Claim 12, Yang discloses (Figs. 3B and 6) the memory device of claim 11, further comprising: an insulating layer (148, first capping insulating layer, Para [0070]) on the cell area, the cell wiring area, and the through-hole wiring area (148 is on A1, cwa, and twa); and an upper wiring (194a, first internal peripheral connection wiring line, Para [0093]) on the insulating layer (194a is on 148), wherein the upper wiring electrically connects the part of the word line patterns and the at least one of the second contact plugs (194a is connected to 193w which connects to 170 and also connected to 180, Para [0093]). Claim 13, Yang discloses (Figs. 3B and 6) the memory device of claim 1, further comprising: a lower transistor (PTR, peripheral transistors, Para [0143]) connected with the first contact plugs (189) and the second contact plugs (PTR is connected to 194a through 80 and 194a is connected to 193w connected to 189 and plug2, Para [0093]). Claim 14, Yang discloses (Figs. 3B and 6) the memory device of claim 13, wherein the lower transistor (PTR) includes a first pass transistor (2nd leftmost PTR, hereinafter “1st”) and a second pass transistor (third leftmost PTR, hereinafter “2nd”), the first pass transistor is connected with the first contact plugs (1st is connected to 194a through plug2 which is connected to 193w and 189, Para [0093]) , the second pass transistor is connected with the at least one of the second contact plugs electrically connected with the part of the word line patterns (2nd is connected to plug2 which is connected to 193w and 170, Para [0093]). Claim 15, Yang discloses (Figs. 3B and 6) the memory device of claim 14, wherein the first pass transistor (1st) is on the cell wiring area (1st is on cwa), and the second pass transistor is on the through-hole wiring area (2nd is on twa). Claim 16, Yang discloses (Figs. 3B and 6) the memory device of claim 14, wherein the first pass transistor and the second pass transistor are on the cell wiring area (left side of 1st and right side of 2nd are on cwa).
Claim 17, Yang discloses (Figs. 3B and 6) the memory device of claim 14, wherein the first pass transistors and the second pass transistor are on the through-hole wiring area (right side of 1st and left side of 2nd are on twa). Claim 18, Yang discloses (Figs. 3B and 6) a memory device comprising: a first semiconductor layer (50, lower substrate may be silicon, Para [0044]) and a second semiconductor layer (103, upper substrate may be polysilicon, Para [0048]) overlapping each other (50 overlaps 103), wherein the first semiconductor layer (50) includes a substrate (50, lower substrate, Para [0044]) including a cell area (A1, first region, Para [0052]) a cell wiring area (second A2 without area around 194a, Para [0052], hereinafter “cwa”) and a through-hole wiring area (area around connection word line 194a, Para [0091], hereinafter “twa”), word line patterns (170, gate horizontal patterns, Para [0051]) on the cell area and the cell wiring area (170 is on A1 and cwa), a channel structure (146c, vertical channel structures, Para [0071]) on the cell area (146c is on A1), first contact plugs (189, gate contact plugs, Para [0090]) on the cell wiring area (189 is on cwa), and second contact plugs (180 of 183a, conductive pillar, Para [0075] multiple shown in Fig. 6, hereinafter “plug2”) on the through-hole wiring area (plug2 is on twa), the word line patterns stacked on the substrate (170 are stacked on 50) and spaced from each other in (170 spaced apart from each other in Z direction) a vertical direction (Z direction), the vertical direction being perpendicular to an upper surface of the substrate (Z direction is perpendicular to upper surface of 50), and the word line patterns extend to the cell wiring area in a direction parallel to the upper surface of the substrate (170 extends to cwa in X direction which is parallel to upper surface of 50);, the channel structure extends in the vertical direction (146c extends in Z direction), the first contact plugs extend in the vertical direction (189 extend in Z direction), each of the first contact plugs is electrically connected with a corresponding one of the word line patterns and insulated from remaining word line patterns other than the corresponding one of the word line patterns (each individual 189 is only connected to a corresponding 170 and thus is insulated from remaining 170s), and the second contact plugs extend in the vertical direction (plug2 extends in Z direction), and at least one of the second contact plugs is electrically connected with a part of the word line patterns (plug2 is connected to 194a through 192a which is then connected to word line connection wire 193w, Para [0090] – [0093]).
Claim 19, Yang discloses (Figs. 3B and 6) a memory device comprising: a first semiconductor layer (103, upper substrate may be silicon, Para [0048]) and a second semiconductor layer (50, lower substrate may be singly crystal silicon, Para [0044]) overlapping each other and being bonded to each other (50 and 44 overlap each other and are bonded though 66), wherein the first semiconductor layer (103) includes: a substrate (103 is upper substrate) including a cell area (A1, first region, Para [0052]), a cell wiring area (second A2 without area around 194a, Para [0052], hereinafter “cwa”), and a through-hole wiring area (area around connection word line 194a, Para [0091], hereinafter “twa”) ; word line patterns (170, gate horizontal patterns, Para [0051]) provided in the cell area and the cell wiring area (170 is provided in A1 and cwa), stacked on the substrate (170 are stacked on 103) to be spaced from each other (170 spaced apart from each other in Z direction) in a vertical direction (Z direction) perpendicular to an upper surface of the substrate (Z direction is perpendicular to upper surface of 103), and extended to the cell wiring area in a direction parallel to the upper surface of the substrate (170 extends to cwa in X direction which is parallel to upper surface of 103); a channel structure (146c, vertical channel structures, Para [0071]) in the cell area (146c is on A1), the channel structure extending in the vertical direction (146c extends in Z direction); first contact plugs (189, gate contact plugs, Para [0090]) extended in the vertical direction in the cell wiring area (189 extends in Z direction in cwa), electrically connected with a corresponding one of the word line patterns (each 189 is connected to a corresponding one of 170), and insulated from remaining word line patterns other than the corresponding one of the word line patterns (each individual 189 is only connected to a corresponding 170 and thus is insulated from remaining 170s); and second contact plugs (180 of 183a, conductive pillar, Para [0075] multiple shown in Fig. 6, hereinafter “plug2”) provided in the through-hole wiring area (plug2 is provided in twa) and extended in the vertical direction (plug2 extends in Z direction), wherein the second semiconductor layer (50) includes a driving circuit (50 includes 80 which has row decoder 3 which has driver, Para [0031], [004] – [0045] electrically connected with the word line patterns (80 connects to plug2 which connects to 194a and word line connection wiring line 193w, Para [0093]), and wherein at least one of the second contact plugs (plug2) is electrically connect with a part of the word line patterns (plug2 us connected to 194a which is connected to word line connection wiring line 193w, Para [0093]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2020/0027893) as applied to claim 6 above, and further in view of Choe (US 2012/0140562). Claim 8, Yang discloses the memory device of claim 6. Yang does not explicitly disclose wherein the word line patterns further includes at least one of: a gate induced drain leakage line adjacent to the string selection line; and a dummy line adjacent to the plurality of word lines. However, Choe discloses (Figs. 4 and 6) wherein word line patterns (Fig. 4, CM1-CM8, conductive materials, Para [0127]) further includes at least one of: a gate induced drain leakage line (DWL2, second dummy word line can function with gate induced drain leakage, Para [0116]) adjacent to (DWL2 is adjacent to SSL1) a string selection line (SSL1, string selection line, Para [0141]); and a dummy line (DWL1, dummy word line, Para [0155]) adjacent (DWL1 is adjacent to WL1/WL2) to a plurality of word lines (WL1/WL2, word lines, Para [0155]). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the dummy word line DWL2 of Choe to the word line patterns 170 of Yang as it can help inhibit drain leakage (Choe, Para [0116]). Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2020/0027893) as applied to claim 19 above, and further in view of Lim (US 2020/0194453). Claim 20, Yang discloses the memory device of claim 19. Yang does not explicitly disclose wherein the first semiconductor layer includes a plurality of first semiconductor layers, wherein the plurality of first semiconductor layers include a first lower semiconductor layer on the second semiconductor layer and a first upper semiconductor layer provided on the first lower semiconductor layer. However, Lim discloses (Fig. 6A) wherein a first semiconductor layer (201, upper substrate, Para [0053]) includes a plurality of first semiconductor layers (201 can be multiple 201a-201c which may be polysilicon, Para [0055]), wherein the plurality of first semiconductor layers (201a-201c) include a first lower semiconductor layer (201a) on (201a is on 101) a second semiconductor layer (101, lower substrate which is semiconductor, Para [0046]) and a first upper semiconductor layer (201b) provided on the first lower semiconductor layer (201b is on 201a). Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply as the plurality of layers may provide extra stability preventing structures from collapsing during manufacturing (Lim, Para [0123]).
Allowable Subject Matter
Claim 9 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Yang (US 2020/0027893), Choe (US 2012/0140562), Lim (US 2020/0194453), fail to disclose (by themselves or in combination) the following limitations in combination with the rest of the claim:
Regarding Claim 9, the corresponding one of the second contact plugs and the other second contact plug are different from each other among the second contact plugs.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO G RAMALLO whose telephone number is (571)272-9227. The examiner can normally be reached Monday-Friday 10am - 6pm.
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/G.G.R/Examiner, Art Unit 2812