DETAILED ACTION
Table of Contents
I. Notice of Pre-AIA or AIA Status 3
II. Election/Restrictions 3
III. Specification 3
IV. Claim Rejections - 35 USC § 112 3
A. Claims 1-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. 4
V. Claim Rejections - 35 USC § 102 4
A. Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0259839 (“Ryu”). 4
VI. Pertinent Prior Art 8
Conclusion 8
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I. Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
II. Election/Restrictions
Applicant’s election without traverse of invention group I, claims 1-12 in the reply filed on 12/02/2025 is acknowledged.
The claims drawn to the non-elected invention group II drawn to the process may be entitled to rejoinder under the conditions explained in the Requirement for Election/Restriction at pages 4-5.
III. Specification
The disclosure is objected to because of the following informalities:
In paragraph [0041] at page 17, line 1, the specification states, “ruthenium oxide (Lu2O3)”. The chemical symbol for ruthenium is Ru, and the chemical symbol Lu is assigned to the chemical element, lutetium. With “ruthenium” is incorrect or “Lu2O3” is incorrect.
Appropriate correction is required.
IV. Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
A. Claims 1-12 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claim 1 recites the limitation “the dipole inducing element” in lines 9 and 11. There is insufficient antecedent basis for this limitation in the claim.
V. Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
A. Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2019/0259839 (“Ryu”).
With regard to claim 1, Ryu discloses, generally in Figs. 10A-10B, 12A-12G, and 23,
1. A semiconductor device, comprising:
[1] a gate trench 105, 15 [¶¶ 61, 184] formed in a substrate 101, 11 [¶¶ 57, 94];
[2] a gate dielectric layer 106, 16 [¶¶ 106, 185-186] covering sidewalls and a bottom surface of the gate trench 105, 15;
[3a] first 108, 18 [¶¶ 170, 101] and second 310, 20 gate electrodes [¶¶ 170, 188-189] positioned over the gate dielectric layer 106, 16,
[3b] the first 108, 18 and second 310, 20 gate electrodes filling a lower portion of the gate trench 105, 15;
[4a] a dipole inducing portion 309, 51L(51A) [¶¶ 169-176, 183, 185] positioned between the second gate electrode 310, 20 and the gate dielectric layer 106, 16,
[4b] the dipole inducing element 309, 51L(51A) including a dipole bond [lanthanum silicate (¶ 174)] and a non-dipole bond [e.g. La-F; see explanation below]; and
[5] a capping layer 111, 21 [¶¶ 170, 194-195] positioned over the dipole inducing element 309, 51L and the second gate electrode 310, 20 wherein the capping layer 111, 21 fills an upper portion of the gate trench 105, 15.
With regard to feature [4b] of claim 1, Ryu states that “FIGS. 12A to 12G illustrate an example of a method for fabricating the semiconductor device 300” (¶ 183) shown in Figs. 10A-10B. Particularly, Figs. 12A-12G show how the upper or “second gate” 20 and dipole-inducing portion 51L are formed. Ryu explains that an anneal is performed to diffuse the dipole-inducing material, e.g. La2O3, of the dipole-inducing layer 51A to form the lanthanum-diffused SiO2, i.e. a lanthanum silicate (¶ 174), that is the dipole-inducing layer 51L (Fig. 12B; ¶ 186). After the anneal, the remaining dipole-inducing material layer 51A is removed by wet etching with HCl/HF (Figs. 12B-12C; ¶ 187). The dipole-inducing layer 51L is again exposed to HF during the etch back of the dipole-inducing layer 51L shown in Figs. 12D-12F uses HCl/HF (¶ 190). Thus, the dipole-inducing layer 51L is at least twice exposed to a source of fluorine. The dipole-inducing layer 51L shown in Figs. 12A-12G equates to the dipole-inducing layer 309 shown in Figs. 10A-10B and 23.
The Instant Application explains that, in order to avoid including fluorine in the TiN, that even cleaning with a fluorine-containing compound would introduce residual fluorine:
In particular, according to an embodiment of the present invention, in order to form fluorine-free titanium nitride (TiN), titanium nitride (TiN) may be included using a fluorine-free source gas. Also, cleaning processes using fluorine may be skipped in the cleaning processes that are performed before and after the formation of the first gate electrode 17[20A].
(¶¶ 40, 47; emphasis added)
The Instant Application further explains that when the cleaning process is not skipped, residual impurities, i.e. fluorine, remains:
[0056] According to another comparative example, when the cleaning process containing impurities is not skipped but performed before and after the formation of the first and second gate electrodes 17 and 20, the impurities remaining on the surface of the gate dielectric layer 16 may form unnecessary bonds on the entire surface of the gate dielectric layer 16 by reacting with the dipole-inducing chemical species that is diffused during the formation of the dipole inducing layer 19 (see FIG. 3H). Since the non-dipole bonds between the dipole-inducing chemical species and the impurities is very strong and it is difficult to remove the non-dipole bonds, there may be residues still remaining even after the removal process, and the remaining residues may cause a short between the buried gates and the bit line contacts.
(Instant Specification: ¶ 56; emphasis added)
Thus, it is held, absent evidence to the contrary that the two exposures of the dipole-inducing layer 51L in Ryu will inherently result in La-F bonds in said dipole-inducing layer 51L from residual fluorine from the HCl/HF cleaning, as evidenced by admissions in the Instant Application (id.). As explained in the Instant Application, the La-F bonds are the claimed “non-dipole bond”. (See at least instant claims 6-8.)
This is all of the features of claim 1.
With regard to claims 2-5, Ryu further discloses,
2. The semiconductor device of claim 1, wherein the dipole bond [e.g. lanthanum silicate (¶ 174)] includes a product of reaction between dipole-inducing chemical species [e.g. La] and the gate dielectric layer 106, 16 [¶ 174].
3. The semiconductor device of claim 2, wherein the dipole-inducing chemical species includes lanthanum (La) [¶ 174].
4. The semiconductor device of claim 1, wherein the gate dielectric layer 106, 16 includes silicon oxide [¶ 174; also ¶¶ 66, 80, 98(first sentence)].
5. The semiconductor device of claim 1, wherein the dipole bond is lanthanum (La) silicate [¶ 174].
With regard to claims 6-8, Ryu further discloses,
6. The semiconductor device of claim 1, wherein the non-dipole bond [e.g. La-F] includes a product of reaction between dipole-inducing chemical species [e.g. La] and an impurity [F from HF exposure during etching, as explained under claim 1].
7. The semiconductor device of claim 6, wherein the impurity includes fluorine [from HF exposure during etching, as explained under claim 1].
8. The semiconductor device of claim 6, wherein the non-dipole bond includes a lanthanum-fluorine (La-F) bond [as explained under claim 1].
With regard to claims 9 and 10, Ryu further discloses,
9. The semiconductor device of claim 1, wherein the first 708 and second 310 gate electrodes include titanium nitride [Fig. 23; ¶¶ 272-273].
10. The semiconductor device of claim 1, wherein the first 708 and second 310 gate electrodes include impurity-free titanium nitride [Fig. 23; ¶¶ 272-273].
With regard to claim 11, Ryu further discloses,
11. The semiconductor device of claim 1, further comprising: first 112, 22 and second 113, 23 doped regions [¶¶ 170, 195] that are formed in the substrate 101, 11 and are spaced apart from each other by the gate trench 105, 15.
With regard to claim 12, Ryu further discloses,
12. The semiconductor device of claim 1, further comprising: a high work function layer 107, 17 [¶¶ 68-69, 184] between the first gate electrode 108, 18 and the gate dielectric layer 106, 16.
VI. Pertinent Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 2023/0009485 (“Lee”) is cited for teaching F-La and La-O bonds in a dipole-inducing layer of a gate dielectric 392, the F-La bonds coming from a fluorine treatment 610 (¶¶ 114-123; Fig. 44). See Figs. 43-49 and paragraphs [0114]-[0139], especially [0132].
US 2011/0254062 (“Shimizu”) is cited for teaching a gate dielectric having a dipole formed by Ge and F at the interface 7 between the SiO2 layer 4 and the high-k HfSiON layer 8 (Fig. 11C; ¶ 136). See also Figs. 3A, 4C, and 10B and associated text.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIK KIELIN whose telephone number is (571)272-1693. The examiner can normally be reached Mon-Fri: 10:00 AM-7:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Wael Fahmy can be reached on 571-272-1705. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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Signed,
/ERIK KIELIN/
Primary Examiner, Art Unit 2814