DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This action is responsive to the amendment received with the response to restriction requirement received on October 20, 2025. Claims 1-11 are canceled. Claims 21-31 are newly added. No claims are amended. Claims 12-31 are currently pending in the application.
Election/Restrictions
Applicant’s election without traverse of Group II in the reply filed on October 20, 2025 is acknowledged.
Applicant has canceled the non-elected claims so no claims are withdrawn.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 20, 2024 is being considered by the examiner.
Drawings
The drawings are objected to because every line, number and letter is not durable, clean, sufficiently dark and dense and uniformly thick and well defined. Specifically, each of figures 1-31 have numerous varying line weights, with lots of different thicknesses, shading, and many of the drawings are illegible. The weight of all lines and letters is not durable enough to permit adequate reproduction, see 37 CFR 1.84(l). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as amended. If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either Replacement Sheet or New Sheet pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 16, 17, 19-22, 25-29 and 31 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gothoskar et al. (US Patent Application Publication US 2005/0189591, hereinafter referred to as “Gothoskar”) in view of Chen et al. (US Patent 10,133,098, hereinafter referred to as “Chen”).
With respect to claim 16, Gothoskar discloses:
A method of fabricating a photonic device (see figure 1, the SOI structure 10 is interpreted as the photonic device), comprising:
providing (etching is not disclosed by Gothoskar, as will be addressed below) a silicon-on-insulator substrate (SOI layer 16 is interpreted as the silicon-on-insulator substrate) to form a first terminal comprising silicon (SOI layer 16 comprises silicon, see paragraph 0026, and is interpreted as forming part of the first terminal) and a waveguide structure (a slab waveguide is formed in the SOI structure, shown in figure 1 guiding collimated beam “O”, see paragraph 0030) connected with the first terminal (see figures 1 and 2; the waveguide portion shown in the figures is interpreted as being connected with the first terminal);
forming a cladding dielectric layer around the first terminal and the waveguide structure (the insulating layer 26, see figures 1 and 2 and paragraph 0026, is interpreted as the cladding dielectric layer as it provides lateral confinement of an optical mode as a cladding, and is made of an insulating dielectric);
forming a capacitor dielectric layer (the thin oxide/gate oxide 18 is interpreted as the capacitor dielectric layer – see paragraph 0026 – further, see the abstract for the specific teaching that this device forms a capacitive structure) over the first terminal (see figure 1);
forming a polysilicon layer (polysilicon layer 20 is interpreted as the polysilicon layer, see paragraph 0026) over the capacitor dielectric layer (see figure 1); and
forming the polysilicon layer and the capacitor dielectric layer to form a second terminal comprising polysilicon (20) and an insulator (gate oxide 18 is interpreted as the insulator) comprising a portion of the capacitor dielectric layer disposed between the first terminal and the second terminal (see figure 1).
Gothoskar further makes numerous references to conventional CMOS processing techniques for use in the manufacturing of the device (see for example paragraphs 0008, 0026, 0030, 0033, 0049, 0057, and 0068), however, Gothoskar does not specifically disclose etching as one of these conventional CMOS techniques and therefore does not disclose that the first terminal and second terminal are formed via etching as required in the claim.
Chen discloses a related MOS capacitor optical modulator (see the title) that includes a waveguide (waveguide structure 110, interpreted as part of a first terminal) and discloses the use of etching in the forming of this structure (see column 4, lines 19-31 and Chen’s claim 20) as a known method for forming waveguides from semiconductor layers having the benefit of low cost of manufacturing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Chen with respect to using etching in the formation of the first and second terminals, in the device of Gothoskar, because etching is a low cost manufacturing method.
With respect to claim 17, the Gothoskar and Chen combination device discloses the limitations of claim 16 as previously stated. Gothoskar further discloses doping the first terminal with a p-type dopant and doping the second terminal with an n-type dopant such that the first terminal, the second terminal, and the insulator form a semiconductor- insulator-semiconductor capacitor (see paragraph 0030 and abstract).
Gothoskar is further silent to the limitation of forming the first terminal, the second terminal, and the insulator to comprise a length along an optical propagation direction that is in a range from approximately 150 microns to approximately 300 microns. However, motivated by a desire to create a device of useful length, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the Gothoskar and Chen combination device such that the first terminal, the second terminal, and the insulator to comprise a length along an optical propagation direction that is in a range from approximately 150 microns to approximately 300 microns, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (In re Aller, 105 USPQ 233) and since such a modification would have involved a mere change in the size of a component, and a change in size is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237,CCPA 1955).
With respect to claims 19 and 20, Gothoskar and Chen disclose the limitations of claims 16 and 17 as previously stated. Gothoskar is further silent to forming an oxide layer over the semiconductor-insulator-semiconductor capacitor; etching the oxide layer to form via cavities respectively over the first terminal and the second terminal; and filling the via cavities with an electrically conducting material to thereby form a first electrically conducting via and a second conducting via respectively electrically coupled to the first terminal and the second terminal (claim 19);
further comprising forming an electrical interconnect structure comprising a first electrically conducting line electrically coupled to the first electrically conducting via and a second electrically conducting line electrically coupled to the second electrically conducting via (claim 20).
The examiner takes official notice that forming oxides layers, etching vias to form cavities and filling these cavities with conductive material, and forming electrical interconnect structures using lines and vias to connect terminals of optical modulators are well known in the optical communication arts and beneficially allow the optical device to be driven with electrical signals run on other semiconductor layers making the devices more compact.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the combination device of Gothoskar and Chen as required in claims 19 and 20, as all the electrical interconnect and via structures are well known, and they beneficially allow the optical device to be driven with electrical signals run on other semiconductor layers making the devices more compact.
With respect to claim 21, Gothoskar discloses:
A method of fabricating a photonic device (see figure 1, the SOI structure 10 is interpreted as the photonic device), comprising:
providing a silicon-on-insulator substrate (SOI layer 16 is interpreted as the silicon-on-insulator substrate);
forming a core (a slab waveguide is formed in the SOI structure, shown in figure 1 guiding collimated beam “O”, see paragraph 0030, is interpreted as the core) comprising:
providing (etching is not disclosed by Gothoskar, as will be addressed below) the silicon-on-insulator substrate to form a silicon portion of the core;
forming an oxide layer (the thin oxide/gate oxide 18 is interpreted as the oxide layer – see paragraph 0026) over the silicon portion of the core; and
forming a polysilicon portion (polysilicon layer 20 is interpreted as the polysilicon portion, see paragraph 0026) of the core over the oxide layer;
forming a cladding dielectric layer (the insulating layer 26, see figures 1 and 2 and paragraph 0026, is interpreted as the cladding dielectric layer as it provides lateral confinement of an optical mode as a cladding, and is made of an insulating dielectric) around the core;
wherein the silicon portion extends to a first terminal (the electrode 22 and heavily-doped region 23 are together interpreted as the first terminal) and the polysilicon portion extends to a second terminal (the electrode 24 and heavily-doped region 25 are together interpreted as the second terminal), wherein the oxide layer is disposed between the silicon portion and the polysilicon portion (see figure 1).
Gothoskar further makes numerous references to conventional CMOS processing techniques for use in the manufacturing of the device (see for example paragraphs 0008, 0026, 0030, 0033, 0049, 0057, and 0068), however, Gothoskar does not specifically disclose etching as one of these conventional CMOS techniques and therefore does not disclose the silicon portion formed via etching as required in the claim.
Chen discloses a related MOS capacitor optical modulator (see the title) that includes a waveguide (waveguide structure 110, interpreted as part of a first terminal) and discloses the use of etching in the forming of this structure (see column 4, lines 19-31 and Chen’s claim 20) as a known method for forming waveguides from semiconductor layers having the benefit of low cost of manufacturing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Chen with respect to using etching in the formation of the silicon portion, in the device of Gothoskar, because etching is a low cost manufacturing method.
With respect to claim 22, the Gothoskar and Chen combination device discloses the limitations of claim 21 as previously stated.
Gothoskar further discloses wherein the silicon-on-insulator substrate comprises a top silicon layer (SOI layer 16 is interpreted as the top silicon layer, see paragraph 0026), a buried oxide layer (insulating layer 14, of the SOI is interpreted as the buried oxide layer) and a bulk silicon layer (silicon substrate 12 is interpreted as the bulk silicon layer).
Gothoskar is silent to the silicon layer having a thickness of approximately 305 nm and the buried oxide layer having a thickness of approximately 2.5 microns.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the Gothoskar and Chen combination device such that the silicon layer having a thickness of approximately 305 nm and the buried oxide layer having a thickness of approximately 2.5 microns since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (In re Aller, 105 USPQ 233) and since such a modification would have involved a mere change in the size of a component, and a change in size is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237,CCPA 1955).
With respect to claim 25, the Gothoskar and Chen combination discloses the limitations of claim 21 as previously stated. Gothoskar further discloses wherein forming the polysilicon portion comprises depositing a polysilicon layer (see figure 1). Gothoskar is silent to the polysilicon layer having a thickness in a range from approximately 90 nm to 135 nm. However, motivated by a desire to create a device with acceptable functionality and of a desired size, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the layer in the claimed range, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (In re Aller, 105 USPQ 233) and since such a modification would have involved a mere change in the size of a component, and a change in size is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237,CCPA 1955).
With respect to claims 26 and 27, the Gothoskar and Chen combination discloses the limitations of claim 21 as previously stated. Gothoskar further discloses doping: the first terminal with a first type dopant; and the second terminal with a second type dopant, wherein the first type dopant is different from the second type dopant (see paragraph 0030) and wherein doping the first terminal includes masking the silicon portion of the core; and doping the second terminal includes masking the polysilicon portion of the core (see paragraph 0030).
With respect to claims 28 and 29, Gothoskar and Chen disclose the limitations of claim 27 as previously stated. Gothoskar is further silent to forming holes in a resistive protective oxide (RPO) wherein the RPO is disposed on the first terminal, the second terminal, the core after the doping; wherein metal ions are deposited through the holes. The examiner takes official notice that forming oxides layers, interpreted as resistive protective oxide layers, etching vias, interpreted as holes, to form cavities and filling these cavities with conductive material, wherein metal ions are deposited through the holes, and forming electrical interconnect structures using lines and vias to connect terminals of optical modulators are well known in the optical communication arts and beneficially allow the optical device to be driven with electrical signals run on other semiconductor layers making the devices more compact.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the combination device of Gothoskar and Chen as required in claims 28 and 29, as all the electrical interconnect through RPO and via/hole structures are well known, and they beneficially allow the optical device to be driven with electrical signals run on other semiconductor layers making the devices more compact.
With respect to claim 31, the Gothoskar and Chen combination discloses the limitations of claim 21 as previously stated. Gothoskar is further silent that the first terminal, the second terminal, and the oxide layer form a semiconductor-insulator-semiconductor capacitor having a length along an optical propagation direction in a range from 150 microns to 300 microns. However, motivated by a desire to create a device of useful length, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the Gothoskar and Chen combination device such that the first terminal, the second terminal, and the insulator to comprise a length along an optical propagation direction that is in a range from approximately 150 microns to approximately 300 microns, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (In re Aller, 105 USPQ 233) and since such a modification would have involved a mere change in the size of a component, and a change in size is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237,CCPA 1955).
Claim(s) 12, 14, 15, 18, 23 and 24 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gothoskar et al. (US Patent Application Publication US 2005/0189591, hereinafter referred to as “Gothoskar”) in view of Chen et al. (US Patent 10,133,098, hereinafter referred to as “Chen”), and further in view of Yoneda et al. (US Patent 8,811,830, hereinafter referred to as “Yoneda”).
With respect to claim 12, Gothoskar discloses:
A method of fabricating a photonic device (see figure 1, the SOI structure 10 is interpreted as the photonic device), comprising:
providing (etching is not disclosed by Gothoskar, as will be addressed below) a silicon-on-insulator substrate (SOI layer 16 is interpreted as the silicon-on-insulator substrate) to form a first terminal comprising silicon (SOI layer 16 comprises silicon, see paragraph 0026, and is interpreted as forming part of the first terminal) and a waveguide structure (a slab waveguide is formed in the SOI structure, shown in figure 1 guiding collimated beam “O”, see paragraph 0030) connected with the first terminal (see figures 1 and 2; the waveguide portion shown in the figures is interpreted as being connected with the first terminal);
forming a cladding dielectric layer around the first terminal and the waveguide structure (the insulating layer 26, see figures 1 and 2 and paragraph 0026, is interpreted as the cladding dielectric layer as it provides lateral confinement of an optical mode as a cladding, and is made of an insulating dielectric);
forming a capacitor dielectric layer (the thin oxide/gate oxide 18 is interpreted as the capacitor dielectric layer – see paragraph 0026 – further, see the abstract for the specific teaching that this device forms a capacitive structure) over the first terminal (see figure 1) that has a thickness and a dielectric constant (these are physical properties present in the layer);
forming a second terminal comprising polysilicon (polysilicon layer 20 is interpreted as the second terminal comprising polysilicon, see paragraph 0026) over the capacitor dielectric layer (see figure 1); and
doping the first terminal with a p-type dopant and doping the second terminal with an n-type dopant (see paragraph 0030).
Gothoskar further makes numerous references to conventional CMOS processing techniques for use in the manufacturing of the device (see for example paragraphs 0008, 0026, 0030, 0033, 0049, 0057, and 0068), however, Gothoskar does not specifically disclose etching as one of these conventional CMOS techniques and therefore does not disclose that the first terminal is formed via etching as required in the claim.
Chen discloses a related MOS capacitor optical modulator (see the title) that includes a waveguide (waveguide structure 110, interpreted as part of a first terminal) and discloses the use of etching in the forming of this structure (see column 4, lines 19-31 and Chen’s claim 20) as a known method for forming waveguides from semiconductor layers having the benefit of low cost of manufacturing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Chen with respect to using etching in the formation of the semiconductor layers, in the device of Gothoskar, because etching is a low cost manufacturing method.
The Gothoskar and Chen combination device is further silent to the capacitor dielectric layer having a dielectric constant that is in a range from approximately 5.0 to 6.8.
Yoneda discloses an optical device comprising an optical waveguide core layer (23) and further includes dielectric insulating films (insulating films 26-28, see column 9, lines 15-38) that can be made from silicon oxynitride (SiON) (see column 9, lines 15-38) which has a dielectric constant that is in a range from approximately 5.0 to 6.8 (per the instant disclosure).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the dielectric insulating layers of the Gothoskar and Chen combination device from SiON, as disclosed as a suitable material for such a purpose by Yoneda, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Lastly, the combination device of Gothoskar, Chen, and Yoneda are silent to the capacitor dielectric layer having a thickness in a range from approximately 1.5nm to 4.5nm. However, since the thickness of the dielectric layer would impact the capacitance and functionality of the device, the thickness of the dielectric layer is interpreted as a results effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to attempt to form the device with various thicknesses of the dielectric layer, including having a thickness in a range from approximately 1.5nm to 4.5nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
With respect to claim 14, the combination device of Gothoskar, Chen, and Yoneda disclose the limitations of claim 12 as previously stated.
Gothoskar further discloses wherein forming the second terminal further comprises: forming a polysilicon layer (20) over the capacitor dielectric layer;
Gothoskar is further silent to the limitation etching the polysilicon layer and the capacitor dielectric layer to form the second terminal comprising the polysilicon and an insulator comprising a portion of the capacitor dielectric layer disposed between the first terminal and the second terminal.
Chen, as previously discussed, discloses the use of etching in the forming of this structure (see column 4, lines 19-31 and Chen’s claim 20) as a known method for forming semiconductor layers having the benefit of low cost of manufacturing.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to utilize the teachings of Chen with respect to using etching in the formation of the semiconductor layers, in the combination device because etching is a low cost manufacturing method.
With respect to claim 15, the combination device of Gothoskar, Chen, and Yoneda disclose the limitations of claim 14 as previously stated. Gothoskar is further silent to forming the first terminal, the second terminal, and the insulator such that: the first terminal comprises a thickness that is in a range from approximately 125 nm to approximately 180 nm; the second terminal comprises a thickness that is in a range from approximately 85 nm to approximately 140 nm; and the insulator comprises a thickness that is in a range from approximately 1.5 nm to 4.5 nm. However, motivated by a desire to create a device with acceptable functionality and of a desired size, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the layers in the claimed ranges, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art (In re Aller, 105 USPQ 233) and since such a modification would have involved a mere change in the size of a component, and a change in size is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237,CCPA 1955).
With respect to claim 18, Gothoskar and Chen disclose that limitations of claim 16 as previously stated. Gothoskar is further silent to wherein forming the capacitor dielectric layer further comprises forming a SiON layer having a dielectric constant that is in a range from approximately 5.0 to 6.8.
Yoneda discloses an optical device comprising an optical waveguide core layer (23) and further includes dielectric insulating films (insulating films 26-28, see column 9, lines 15-38) that can be made from silicon oxynitride (SiON) (see column 9, lines 15-38) which has a dielectric constant that is in a range from approximately 5.0 to 6.8 (per the instant disclosure).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the dielectric insulating layers of the Gothoskar and Chen combination device from SiON, as disclosed as a suitable material for such a purpose by Yoneda, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
With respect to claims 23 and 24, the Gothoskar and Chen combination discloses the limitations of claims 21 as previously stated. Gothoskar is silent to wherein the oxide layer includes a silicon oxynitride layer having a thickness in a range from approximately 1.5 nm to 4.5 nm; wherein the oxide layer includes a dielectric constant in a range from approximately 5.0 to 6.8.
Yoneda discloses an optical device comprising an optical waveguide core layer (23) and further includes dielectric insulating films (insulating films 26-28, see column 9, lines 15-38) that can be made from silicon oxynitride (SiON) (see column 9, lines 15-38) which has a dielectric constant that is in a range from approximately 5.0 to 6.8 (per the instant disclosure).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the dielectric insulating layers of the Gothoskar and Chen combination device from SiON, as disclosed as a suitable material for such a purpose by Yoneda, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Lastly, the combination device of Gothoskar, Chen, and Yoneda are silent to the capacitor dielectric layer having a thickness in a range from approximately 1.5nm to 4.5nm. However, since the thickness of the dielectric layer would impact the capacitance and functionality of the device, the thickness of the dielectric layer is interpreted as a results effective variable. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to attempt to form the device with various thicknesses of the dielectric layer, including having a thickness in a range from approximately 1.5nm to 4.5nm, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Allowable Subject Matter
Claim 13 and 30 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the prior art of record, which is the closest prior art to the subject matter of the claims, does not disclose the limitations “wherein forming the capacitor dielectric layer further comprises performing operations comprising:generating a gate oxide layer over the first terminal by performing an in-situ stream generation oxidation process or a rapid thermal oxidation process on the silicon of the first terminal;introducing nitrogen into the gate oxide layer to generate a SiON layer by performing a decoupled plasma nitridation process; andannealing the SiON layer by performing a post nitridation anneal process such that the capacitor dielectric layer comprises an annealed SiON layer” (claim 13) or wherein self-aligned silicides are formed through the holes” (claim 30). There is nothing on the record that would suggest such differences would be obvious to one having ordinary skill in the art before the effective filing date of the claimed invention. Lastly, one having ordinary skill in the art does not possess any general knowledge or known motivations to find such differences obvious in view of the prior art of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN M BEDTELYON whose telephone number is (571)270-1290. The examiner can normally be reached 8:00am - 4:30pm.
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/John Bedtelyon/Primary Examiner, Art Unit 2874
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