DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) rejected have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6 and 21-28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. 20180053906.
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Regarding claim 1, fig. 2 of Lee discloses a display device comprising:
a display region DA;
a first wire region (as labeled by examiner above) extending in a direction from a side of the display region;
a second wire region (as labeled by examiner above) extending in the direction from the first wire region;
a peripheral region (as labeled by examiner above) surrounding the display region, the first wire region, and the second wire region;
a pixel structure (see structure of 210/300) disposed on a substrate in the display region;
a first wire part (second conductive layer part – par [0057]) disposed on the substrate in the first wire region, and including first wires 213a(s) electrically connected to the pixel structure (par [0058] - 213a located in the first region 1A may be electrically connected to a TFT or the like within the display region DA);
an inorganic insulating layer 130 (par [0037]) covering the first wire part;
a second wire part (first conductive layer – par [0051]) disposed on the inorganic insulating layer in the second wire region, and including second wires 215c(s) electrically contacting the first wires through first through-holes (par [0057] - first conductive layer 215c contacts each of the second conductive layers 213a and 213b through a contact hole formed in the interlayer insulating film 130 and fig. 3 shows a plurality of 215c meaning plurality of contact holes) formed through the inorganic insulating layer and arranged along a boundary between the first wire region and the second wire region, respectively;
an organic insulating layer 140 (par [0039]) covering the second wire part; and
a protective layer (as labeled by examiner above – dotted line region) disposed on the organic insulating layer, and at least partially overlapping the first through-holes in a plan view (this is necessary the case),
wherein the protective layer is electrically insulated from each of the first wire part and the second wire part.
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Regarding claim 2, fig. 2 of Lee (as labeled by examiner above) discloses further comprising: a sealing region defined by a sealing opening that penetrates the organic insulating layer, and surrounding the display region.
Regarding claim 21 (see rejections of claims 1-2 above), Lee discloses a display device comprising: a display region; a first wire region extending in a direction from a side of the display region; a second wire region extending in the direction from the first wire region; a peripheral region surrounding the display region, the first wire region, and the second wire region; a pixel structure disposed on a substrate in the display region; a first wire part disposed on the substrate in the first wire region, and including first wires electrically connected to the pixel structure; an inorganic insulating layer covering the first wire part; a second wire part disposed on the inorganic insulating layer in the second wire region, and including second wires electrically contacting the first wires through first through-holes formed through the inorganic insulating layer and arranged along a boundary between the first wire region and the second wire region, respectively; an organic insulating layer covering the second wire part; a protective layer disposed on the organic insulating layer, and at least partially overlapping the first through-holes in a plan view; and a sealing region defined by a sealing opening that penetrates the organic insulating layer, and surrounding the display region.
Regarding claims 3 and 22, fig. 2 of Lee discloses wherein the second wire region is spaced apart from the sealing region in a plan view, and a portion of the first wire region overlaps a portion of the sealing region in a plan view.
Regarding claims 4 and 23, fig. 2 of Lee discloses wherein the protective layer covers a portion of a top surface of the inorganic insulating layer exposed by the sealing opening in a region where the portion of the first wire region overlaps the portion of the sealing region in a plan view.
Regarding claims 6 and 25, fig. 2 of Lee discloses further comprising: a sealing member 410 disposed within the sealing opening; and a cover member 520 supported by the sealing member.
Regarding claim 24, fig. 2 of Lee discloses wherein the protective layer overlaps at least a portion of a sidewall of the sealing opening in a plan view.
Regarding claim 26, fig. 2 of Lee discloses wherein the protective layer is spaced apart from each of the second wire part and the first through-holes by the organic insulating layer.
Regarding claim 27, fig. 2 of Lee discloses wherein the second wire part is disposed directly on a top surface of the inorganic insulating layer at locations (region 2A) external to the first through-holes in a plan view.
Regarding claim 28, par [0058] of Lee discloses wherein the first wire part and the second wire part are electrically connected to a data line that transmits a data signal to the pixel structure.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee.
Regarding claim 7, fig. 2 of Lee discloses wherein the pixel structure includes:
a semiconductor layer 211 disposed on the substrate;
a gate electrode 213 disposed on the semiconductor layer and at least partially overlapping a portion of the semiconductor layer in a plan view (necessary the case), the gate electrode and the first wire part including a same material (213 and 213a both have same layer material);
the inorganic insulating layer 130 covering the gate electrode;
a source-drain electrode disposed on the inorganic insulating layer and electrically contacting another portion of the semiconductor layer, the source-drain electrode and the second wire part including a same material (conductive);
the organic insulating layer covering the source-drain electrode; and
a pixel electrode layer 310 disposed on the organic insulating layer and electrically contacting the source-drain electrode.
Lee does not disclose that the pixel electrode layer and the protective layer including a same material.
However, the court has held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness.
As such it would have been obvious to form a device of Lee comprising that the pixel electrode layer and the protective layer including a same material as there are processing material in the fabrication process that can cross contaminate one another.
Regarding claim 8, Lee necessary discloses wherein the first wire part includes a material having a first resistivity, and wherein the protective layer is spaced apart from each of the second wire part and the first through-holes by the organic insulating layer.
Lee does not disclose that the second wire part includes a material having a second resistivity that is lower than the first resistivity.
However, the court has held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness.
As such it would have been obvious to form a device of Lee comprising that disclose that the second wire part includes a material having a second resistivity that is lower than the first resistivity in order to meet the applicant design choice such RC requirement.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lee et al. 20180145125 (Lee5)
Regarding claim 9, Lee does not disclose further comprising: a first power supply electrode layer disposed on the substrate and adjacent to the side of the display region, and receiving a first power supply voltage; and a second power supply electrode layer disposed on the substrate in the peripheral region, and receiving a second power supply voltage.
However, par [0061] of Lee5 discloses that the controller 80 receives a vertical synchronization signal, a horizontal synchronization signal, and a clock signal and generates control signals for controlling driving of the first and second scan drivers 20 and 30. The generated control signals may be transferred to the first and second scan drivers 20 and 30 respectively via the terminal 43 and the wirings 21 and 31. Scan signals of the first and second scan drivers 20 and 30 are provided to the pixels P via the scan lines SL. Also, the controller 80 provides a driving voltage ELVDD and a common voltage ELVSS to the driving voltage supply line 60 and the common voltage supply line 70 respectively via the terminals 42 and 44 connected to the FPCB and the wirings 61 and 71. The driving voltage ELVDD is provided to each pixel P via a driving voltage line PL, and the common voltage ELVSS may be provided to an opposite electrode of the pixel P.
As such it would have been obvious to form a device of Lee further comprising: a first power supply electrode layer disposed on the substrate and adjacent to the side of the display region, and receiving a first power supply voltage; and a second power supply electrode layer disposed on the substrate in the peripheral region, and receiving a second power supply voltage in order to form a driving voltage and a common voltage such as taught by Lee5.
Regarding claim 10, Lee and Lee5 do not discloses of wherein the first power supply electrode layer and the protective layer include a same material.
However, the court has held that the selection of a known material based on its suitability for its intended use supported a prima facie obviousness.
As such it would have been obvious to form a device of Lee wherein the first power supply electrode layer and the protective layer include a same material as there are processing material in the fabrication process that can cross contaminate one another.
Regard claim 11, fig. 2 of Lee discloses wherein the first power supply electrode layer is electrically insulated from the protective layer, and the second wire part is disposed directly on a top surface of the inorganic insulating layer at locations external to the first through-holes in a plan view (necessary the case).
Allowable Subject Matter
Claim 12 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM EST.
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893