Prosecution Insights
Last updated: April 19, 2026
Application No. 18/302,375

CRITICAL DIMENSION INSPECTION METHOD AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD USING THE SAME

Non-Final OA §102§103
Filed
Apr 18, 2023
Examiner
FRASER, STEWART A
Art Unit
1724
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
2y 7m
To Grant
99%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allow Rate
1135 granted / 1320 resolved
+21.0% vs TC avg
Moderate +14% lift
Without
With
+14.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
45 currently pending
Career history
1365
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
45.2%
+5.2% vs TC avg
§102
24.2%
-15.8% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1320 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This is the initial office action for US Patent Application No. 18/302375 by Kong et al. Claims 1-20 are currently pending and have been fully considered. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4 and 6 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tripodi et al. (US 2019/0378012 A1), herein referred to as Tripodi. Regarding claim 1, Tripodi teaches [0007-0009 and 0111] a method of determining a characteristic of interest relating to a structure on a substrate formed by a lithographic process and measuring the critical dimension of the structure (a method for inspecting a critical dimension). The method taught by Tripodi comprises [0039] applying a photoresist on a substrate, printing a target pattern of different focus values by varying the exposure dose onto the substrate [0117] (variably irradiating a dose of light onto the photoresist), performing an exposure process to develop the photoresist [0041] (photo process on the photoresist, the photo process including developing the photoresist to form a photoresist pattern), forming a plurality of patterned structures on the substrate via etching [0041] (the forming the plurality of patterns including performing an etching process using the photoresist pattern as an etching mask), measuring [0040 and 0111] a width of each of the plurality of patterned structures and a spacing between adjacent ones of the plurality of patterned structures to obtain a measured width and a measured spacing, and identifying [0040] errors in the exposure process (a cause of a defect in the photo process) based on the measured properties (measured width and the measured spacing) of the patterned structures. Regarding claim 2, Tripodi teaches (Figure 11 and [0114]) the substrate includes a plurality of shot areas, each of the plurality of shot areas is a minimum area by which the photoresist is developed, and the variably irradiating the dose of light includes irradiating the dose of light variably onto an entirety of a face of the substrate such that the dose of light is uniformly irradiated onto each of the plurality of shot areas. Regarding claim 3, Tripodi teaches (Figure 11 and [0114]) the variably irradiating the dose of light includes irradiating the dose of light variably onto an entirety of a face of the substrate such that the dose of light is uniformly irradiated onto and along a position spaced apart by a first distance from a center of the substrate. Regarding claim 4, Tripodi teaches (Figure 11 and [0114]) the variably irradiating of the dose of light includes irradiating the dose of light variably onto the entirety of the face of the substrate such that the dose of light is uniformly irradiated onto and along a position spaced apart by a second distance from the center of the substrate, and the first distance and the second distance are different from each other. Regarding claim 6, Tripodi teaches [0040] a cause of a defect in the etching process is not identified based on the measured width and the measured spacing Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 5 and 7-12 are rejected under 35 U.S.C. 103 as being unpatentable over Tripodi et al. (US 2019/0378012 A1), herein referred to as Tripodi in view of Komine (US 2014/0370719 A1). Regarding claim 7, Tripodi teaches [0007-0009 and 0111] a method of determining a characteristic of interest relating to a structure on a substrate formed by a lithographic process and measuring the critical dimension of the structure (a method for inspecting a critical dimension). The method taught by Tripodi comprises [0039] applying a photoresist on a substrate, printing a target pattern of different focus values by varying the exposure dose onto the substrate [0117] (variably irradiating a dose of light onto the photoresist), performing an exposure process to develop the photoresist [0041] (photo process on the photoresist, the photo process including developing the photoresist to form a photoresist pattern), forming a plurality of patterned structures on the substrate via etching [0041] (the forming the plurality of patterns including performing an etching process using the photoresist pattern as an etching mask), measuring [0040 and 0111] a width of each of the plurality of patterned structures and a spacing between adjacent ones of the plurality of patterned structures to obtain a measured width and a measured spacing, and identifying [0040] errors in the exposure process (a cause of a defect in the photo process) based on the measured properties (measured width and the measured spacing) of the patterned structures. Tripodi does not appear to explicitly teach the limitations of claim 7 directed to forming a plurality of second patterns on a first substrate by performing a first photo process under a first condition and an etching process under a second condition. However, from the same field of technology, Komine discloses a method of manufacturing a semiconductor device based on a double exposure process. In view of claim 7, Komine teaches (Claim 18) a method for manufacturing a semiconductor device comprising projecting first and second line-and-space patterns on a first substrate on which a photosensitive material is applied by irradiating exposure light from a first direction that is displaced from an optical axis of an optical system on the first line-and-space pattern having a first pattern pitch and the second line-and-space pattern having a second pattern pitch (forming a plurality of second patterns on a first substrate by performing a first photo process). Komine further teaches projecting a circuit pattern on a second substrate on which a photosensitive material is applied by irradiating exposure light (second photo process) on the circuit pattern formed on a reticle and forming a resist pattern corresponding to the circuit pattern on the second substrate by developing the second substrate. At the time of the filing date of the instant application, it would have been obvious to one of ordinary skill in the art to modify the inspection method taught by Tripodi to include the semiconductor manufacturing method taught by Komine in order to more accurately measure patterns on a semiconductor substrate and to improve inspection of the patterns so that errors can be reduced in the semiconductor manufacturing process. In view of claim 8, the combination of Tripodi and Komine teaches (Tripodi (Figure 11 and [0114] and Komine Figure 1) the second substrate includes a plurality of shot areas, each of the plurality of shot areas is a minimum area by which the photoresist is developed, and the variably irradiating the dose of light includes irradiating the dose of light variably onto an entirety of a face of the substrate such that the dose of light is uniformly irradiated onto each of the plurality of shot areas. In view of claim 9, the combination of Tripodi and Komine teaches (Tripodi (Figure 11 and [0114] and Komine Figure 1) the variably irradiating the dose of light includes irradiating the dose of light variably onto an entirety of a face of the substrate such that the dose of light is uniformly irradiated onto and along a position spaced apart by a first distance from a center of the substrate. In view of claim 10, the combination of Tripodi and Komine teaches (Tripodi (Figure 11 and [0114] and Komine Figure 1) the variably irradiating of the dose of light includes irradiating the dose of light variably onto the entirety of the face of the substrate such that the dose of light is uniformly irradiated onto and along a position spaced apart by a second distance from the center of the substrate, and the first distance and the second distance are different from each other. In view of claims 5 and 11, the combination of Tripodi and Komine teaches (Komine Claim 18) the forming the plurality of first patterns and the forming the plurality of second patterns each include performing a double patterning process or a quadruple patterning process. In view of claim 12, the combination of Tripodi and Komine teaches (Tripodi [0007-0009 and 0111]) obtaining the first condition includes performing the critical dimension inspection method at least once. Claims 14-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tripodi et al. (US 2019/0378012 A1), herein referred to as Tripodi in view of Komine (US 2014/0370719 A1) and Hayano et al. (US Patent 6,548,312 B1), herein referred to as Hayano. Regarding claim 14, Tripodi teaches [0007-0009 and 0111] a method of determining a characteristic of interest relating to a structure on a substrate formed by a lithographic process and measuring the critical dimension of the structure (a method for inspecting a critical dimension). The method taught by Tripodi comprises [0039] applying a photoresist on a substrate, printing a target pattern of different focus values by varying the exposure dose onto the substrate [0117] (variably irradiating a dose of light onto the photoresist), performing an exposure process to develop the photoresist [0041] (photo process on the photoresist, the photo process including developing the photoresist to form a photoresist pattern), forming a plurality of patterned structures on the substrate via etching [0041] (the forming the plurality of patterns including performing an etching process using the photoresist pattern as an etching mask), measuring [0040 and 0111] a width of each of the plurality of patterned structures and a spacing between adjacent ones of the plurality of patterned structures to obtain a measured width and a measured spacing, and identifying [0040] errors in the exposure process (a cause of a defect in the photo process) based on the measured properties (measured width and the measured spacing) of the patterned structures. Tripodi does not appear to explicitly teach the limitations of claim 14 directed to forming a plurality of second patterns on a first substrate by performing a first photo process under a first condition and an etching process under a second condition. However, from the same field of technology, Komine discloses a method of manufacturing a semiconductor device based on a double exposure process. In view of claim 14, Komine teaches (Claim 18) a method for manufacturing a semiconductor device comprising projecting first and second line-and-space patterns on a first substrate on which a photosensitive material is applied by irradiating exposure light from a first direction that is displaced from an optical axis of an optical system on the first line-and-space pattern having a first pattern pitch and the second line-and-space pattern having a second pattern pitch (forming a plurality of second patterns on a first substrate by performing a first photo process). Komine further teaches projecting a circuit pattern on a second substrate on which a photosensitive material is applied by irradiating exposure light (second photo process) on the circuit pattern formed on a reticle and forming a resist pattern corresponding to the circuit pattern on the second substrate by developing the second substrate. The combination of Tripodi and Komine does not appear to explicitly teach the limitations of claim 14 directed to the formation of word line, bit line and dummy patterns during the formation of the plurality of patterns. However, from the same field of technology, Hayano discloses a manufacturing method of semiconductor integrated circuit devices. In view of claim 14, Hayano teaches (Column 18, Lines 3-42 and Figure 22) the formation of a plurality of word line (Figure 22 WL) and bit line (Figure 22 BL) patterns on a substrate. A capacitor 5 is subsequently formed over the bit and word line patterns based on contact holes 7. Hayano also teaches (Figure 2) optical proximity correction involving the use of dummy patterns. At the time of the filing date of the instant application, it would have been obvious to one of ordinary skill in the art to modify the inspection method taught by Tripodi to include the semiconductor manufacturing method taught by Komine and further include the manufacturing method taught by Hayano in order to more accurately measure patterns on a semiconductor substrate and to improve inspection of the patterns so that errors can be reduced in the semiconductor manufacturing process. In view of claim 15, the combination of Tripodi, Komine and Hayano teaches (Tripodi (Figure 11 and [0114] and Komine Figure 1) the second substrate includes a plurality of shot areas, each of the plurality of shot areas is a minimum area by which the photoresist is developed, and the variably irradiating the dose of light includes irradiating the dose of light variably onto an entirety of a face of the substrate such that the dose of light is uniformly irradiated onto each of the plurality of shot areas. In view of claim 16, the combination of Tripodi, Komine and Hayano teaches (Tripodi (Figure 11 and [0114] and Komine Figure 1) the variably irradiating the dose of light includes irradiating the dose of light variably onto an entirety of a face of the substrate such that the dose of light is uniformly irradiated onto and along a position spaced apart by a first distance from a center of the substrate. In view of claim 17, the combination of Tripodi, Komine and Hayano teaches (Tripodi (Figure 11 and [0114] and Komine Figure 1) the variably irradiating of the dose of light includes irradiating the dose of light variably onto the entirety of the face of the substrate such that the dose of light is uniformly irradiated onto and along a position spaced apart by a second distance from the center of the substrate, and the first distance and the second distance are different from each other. In view of claim 18, the combination of Tripodi, Komine and Hayano teaches (Komine Claim 18) the forming the plurality of first patterns and the forming the plurality of second patterns each include performing a double patterning process or a quadruple patterning process. In view of claim 19, the combination of Tripodi, Komine and Hayano teaches (Tripodi [0007-0009 and 0111]) obtaining the first condition includes performing the critical dimension inspection method at least once. Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Tripodi et al. (US 2019/0378012 A1), herein referred to as Tripodi in view of Komine (US 2014/0370719 A1) as applied to claim 7, and further in view of Takagi et al. (US 2005/0270504 A1), herein referred to as Takagi. The combination of Tripodi and Komine does not appear to explicitly teach the limitations of claim 13 directed to the spacing of the line patterns. However, from the same field of technology, Takagi discloses a device fabrication method. In view of claim 13, Takagi teaches [0068-0070] forming line and space patterns wherein a spacing of the line patterns are within 0.3 nm of each other. Takagi further teaches [0072] that patterns of 100 nm or less can be measured with high accuracy. At the time of the filing date of the instant application, it would have been obvious to one of ordinary skill in the art to modify the inspection method taught by Tripodi to include the semiconductor manufacturing method taught by Komine and further include the device fabrication method taught by Takagi in order to more accurately measure patterns on a semiconductor substrate and to improve inspection of the patterns so that errors can be reduced in the semiconductor manufacturing process. Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tripodi et al. (US 2019/0378012 A1), herein referred to as Tripodi in view of Komine (US 2014/0370719 A1) and Hayano et al. (US Patent 6,548,312 B1), herein referred to as Hayano, as applied to claim 14, and further in view of Takagi et al. (US 2005/0270504 A1), herein referred to as Takagi. The combination of Tripodi, Komine and Hayano does not appear to explicitly teach the limitations of claim 20 directed to the spacing of the line patterns. However, from the same field of technology, Takagi discloses a device fabrication method. In view of claim 20, Takagi teaches [0068-0070] forming line and space patterns wherein a spacing of the line patterns are within 0.3 nm of each other. Takagi further teaches [0072] that patterns of 100 nm or less can be measured with high accuracy. At the time of the filing date of the instant application, it would have been obvious to one of ordinary skill in the art to modify the teachings of Tripodi, Komine and Hayano and further include the device fabrication method taught by Takagi in order to more accurately measure patterns on a semiconductor substrate and to improve inspection of the patterns so that errors can be reduced in the semiconductor manufacturing process. Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEWART A FRASER whose telephone number is (571)270-5126. The examiner can normally be reached M-F, 7am-4pm, EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Miriam Stagg can be reached at 571-270-5256. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /STEWART A FRASER/Primary Examiner, Art Unit 1724
Read full office action

Prosecution Timeline

Apr 18, 2023
Application Filed
Jan 21, 2026
Non-Final Rejection — §102, §103
Mar 02, 2026
Interview Requested
Mar 09, 2026
Examiner Interview Summary
Mar 09, 2026
Applicant Interview (Telephonic)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
99%
With Interview (+14.2%)
2y 7m
Median Time to Grant
Low
PTA Risk
Based on 1320 resolved cases by this examiner. Grant probability derived from career allow rate.

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