DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group I, claims 1 – 8, in the reply filed on 11/12/2025 is acknowledged. The traversal is on the grounds that there is no search burden. This is not found persuasive because while a method of manufacturing using CMP reference MAY include teachings directed to inspection and layout, the examiner respectfully disagrees that these references will naturally be found in the CMP manufacturing arts. Additionally, it is entirely conceivable that the inspection and layout methods may be applied to any semiconductor process step, creating a serious search burden for the examiner.
The requirement is still deemed proper and is therefore made FINAL.
Claims 8-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on November 12, 2025.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1 – 8 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2003/0193050) in view of Kim et al. (“Novel Cu/SiCN surface topography control for 1 µm pitch hybrid wafer-to-wafer bonding”, 2020).
Regarding claim 1, Park teaches (FIG. 5):
A method of manufacturing a wafer, the method comprising:
preparing the wafer, including a semiconductor chip region (main region b) and a test region (test region a), such that an integrated circuit is formed in the semiconductor chip region ([0023]);
forming an insulating layer (FIG. 8 pattern 52/58) on an upper surface of the prepared wafer;
forming a pattern (58) in the semiconductor chip region of the insulating layer;
forming a line pattern (FIG. 7, 54b) having a constant line width and a constant pitch in the test region of the insulating layer;
depositing a metal layer (FIG. 9, 60) on the insulating layer;
polishing the metal layer using a chemical mechanical polishing (CMP) process such that bonding pads and metal lines are formed based on the bonding pad pattern and the line pattern, respectively ([0031], FIG. 10);
determining a surface roughness value of the test region by measuring the test region in which the metal lines are formed using an atomic force microscope (AFM) (FIG. 11, 108, “profiler” may be an AFM, while “step size” indicates “roughness”);
determining a step difference value of the bonding pads of the semiconductor chip region with respect to the insulating layer, based on the surface roughness value of the test region (110, [0037], correlating main pattern parameters based on measuring step height of test pattern); and
selectively performing the CMP process when the step difference value of the bonding pads is not within a target step difference tolerance range (112, [0037]).
Park fails to expressly disclose that the main region metal structures are “bonding pads”. However, “bonding pads” is considered an intended use recitation for an exposed metal structure of a semiconductor device. The instant invention is directed to utilizing a test structure as an indicator for process performance on an active device structure. The intended us of the active structure does not convey patentable weight to the subject matter that the claims are directed to. It has been held that a recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus satisfying the claimed structural limitations. Ex parte Masham, 2 USPQ2d 1647 (1987). An intended use or purpose usually will not limit the scope of the claim because such statements usually do no more than define a context in which the invention operates." Boehringer Ingelheim Vetmedica, Inc. v. Schering-Plough Corp., 320 F.3d 1339, 1345 (Fed. Cir. 2003). Although "[s]uch statements often.., appear in the claim's preamble," In re Stencel, 828 F.2d 751,754 (Fed. Cir. 1987), a statement of intended use or purpose can appear elsewhere in a claim.
Further, Kim teaches test structures measured by AFM for controlling Cu/SiCN surface topography for bonding pads. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to apply the test structure monitoring process of Park to the bonding pad forming process of Kim for the predictable advantage of correlating active device structural component process results with readily measurable test structures.
Regarding claim 2, Park teaches ([0026], FIG. 6 – 8):
The manufacturing method of the wafer of claim 1, wherein the integrated circuit comprises logic circuits included in a substrate of the wafer, interconnections connecting the logic circuits, and vias vertically connecting the interconnections, the bonding pads contact the vias, and the metal lines are horizontally separated from the vias.
Regarding claim 3, Kim teaches:
The manufacturing method of the wafer of claim 1, wherein the insulating layer is formed of silicon carbon nitride (SiCN), and at least one of the bonding pads and the metal lines are formed of copper (Cu).
The application of the measurement process of Park to the specific materials of Kim is an obvious intended use recitation.
Regarding claim 4, Kim teaches (III.B. AFM Analysis Method page 217):
The manufacturing method of the wafer of claim 1, wherein the surface roughness value of the test region is determined based on a dispersion of a height value in an overall region of an image measured by the AFM.
Regarding claim 5, Park teaches (FIG. 5, [0023]):
The manufacturing method of the wafer of claim 1, wherein the wafer comprises main chip regions and a scribe lane partitioning the main chip regions, wherein the test region is included in at least one of a portion of the main chip regions or in the scribe lane.
Regarding claim 6, Park teaches ([0037]):
The manufacturing method of the wafer of claim 1, wherein determining the step difference value of the bonding pads comprises determining a step difference value of the metal lines based on the surface roughness value of the test region; and determining the step difference value of the bonding pads based on the determined step difference value of the metal lines.
Regarding claim 7, Kim teaches (IV.B. page 220):
The manufacturing method of the wafer of claim 1, wherein the target step difference tolerance range of the bonding pads is less than a measurable step difference range of the AFM, and a step difference range of the metal lines is within the measurable step difference range of the AFM.
Regarding claim 8, Park teaches (FIG. 10):
The manufacturing method of the wafer of claim 7, wherein the metal lines are recessed with respect to an insulating layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624
Prosecution Insights