DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1 – 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The examiner notes that the newly recited limitations appear to be directed to the “SLIT” separation area at the edges of stacks for isolating the conductive layers from contacting plug 93. Goda is silent regarding any separation areas between banks. However, previously cited Lu et al. (US 2019/0081069) teaches bank separating areas with conductive plugs (FIG. 4C, 424) and which have insulating layers 412 which protrude from and provide isolation from the plug for conductive layers 410.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Goda et al. (US 2021/0202751) in view of Lu et al. (US 2019/0081069).
Regarding claim 1, Goda teaches (FIG. 2H, 3):
A memory device, comprising:
a first interconnect structure (102) located over a substrate ([0028]);
a second interconnect structure (326) located over the first interconnect structure ([0046] – [0047]);
a stacked structure (106/108) located between the first interconnect structure and the second interconnect structure, wherein the stacked structure comprises a plurality of conductive layers and a plurality of insulating layers stacked alternately ([0028]);
a stop layer (128) located between the stacked structure and the second interconnect structure; and
a plurality of channel pillar structures extending through the stacked structure, each channel pillar structure comprising:
a channel pillar (110) extending through the stacked structure and the stop layer;
a first channel plug (122) located at a first end of the channel pillar and connected to the first interconnect structure; and
a second channel plug (124/126) located at a second end of the channel pillar and connected to the second interconnect structure, wherein a bottom surface of the second channel plug is closer to the substrate than a bottom surface of the stop layer (FIG. 2H).
Goda is silent regarding any bank edges and wherein in the stacked structure, sidewalls of the insulating layers are protruded from sidewalls of the conductive layers.
However, Lu et al. (US 2019/0081069) teaches bank separating areas with conductive plugs (FIG. 4C, 424) and which have insulating layers 412 which protrude from and provide isolation from the plug for conductive layers 410.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the isolating edge of bank structures of Lu in the device of Goda for the predictable advantage of enabling a conductive plug through the stack without shorting adjacent conductive layers unintentionally.
Regarding claim 2, Goda teaches (FIG. 2H):
The memory device according to claim 1, wherein the second channel plug extends through the stop layer and at least a portion of a topmost insulating layer of the plurality of insulating layers.
Regarding claim 3, Goda teaches (FIG. 2H):
The memory device according to claim 1, wherein the bottom surface of the second channel plug is located between the bottom surface of the stop layer and a bottom surface of a topmost conductive layer of the plurality of conductive layers.
Regarding claim 4, Goda teaches ([0041]):
The memory device according to claim 1, wherein the first channel plug and the second channel plug comprise semiconductor materials with dopants.
Regarding claim 5, Goda teaches an upper interconnect structure but fails to expressly disclose:
The memory device according to claim 1, wherein adjacent second channel plugs are electrically connected to each other through a semiconductor pad.
However, it would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to include a common semiconductor pad for electrically coupled channels, since applicant has not disclosed that the semiconductor pad solves any stated problem or is for any particular purpose and it appears that the invention would perform equally as well with any structure of common electrical connection.
Regarding claim 6, Goda teaches an upper interconnect structure but fails to expressly disclose:
The memory device according to claim 1, wherein adjacent second channel plugs are connected to the same conductive pad of the second interconnect structure, and then connected to a common source line.
However, it would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to include a common semiconductor pad for electrically coupled channels, since applicant has not disclosed that the semiconductor pad solves any stated problem or is for any particular purpose and it appears that the invention would perform equally as well with any structure of common electrical connection.
Regarding claim 7, Goda teaches (FIG. 3, 326, [0068]):
The memory device according to claim 1, wherein adjacent second channel plugs are connected to multiple vias of the second interconnect structure, and then connected to a common source line.
Regarding claim 8, Goda teaches ([0028]):
The memory device according to claim 1, further comprising a bonding structure located in the first interconnect structure.
Regarding claim 9, Goda teaches an upper interconnect structure and an adjustable depth of a second plug ([0040]) but fails to expressly disclose:
The memory device according to claim 1, wherein a height of the second channel plug from a top surface of the stop layer is in a range from 500 angstroms to 1500 angstroms.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the second channel plug of Goda to a depth which optimizes GIDL performance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 10, Goda teaches an upper interconnect structure and an adjustable depth of a second plug ([0040]) but fails to expressly disclose:
The memory device according to claim 1, wherein an aspect ratio of the second channel plug is in a range from 0.5 to 3.75.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the second channel plug of Goda to a depth which optimizes GIDL performance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 11, Goda teaches an upper interconnect structure and an adjustable depth of a second plug ([0040]) but fails to expressly disclose:
The memory device according to claim 1, wherein a distance between a bottom surface of the second channel plug and a top surface of a topmost conductive layer of the plurality of conductive layers is in a range from -300 angstroms to 300 angstroms.
However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the second channel plug of Goda to a depth which optimizes GIDL performance, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 12, Goda teaches (FIG. 3):
The memory device according to claim 1, further comprising: a plurality of through vias, extending through the stop layer and through intermediate layers and the insulating layers of the stacked structure stacked alternately, and connected to the first interconnect structure and the second interconnect structure.
Regarding claim 13, Goda teaches ([0045]):
The memory device according to claim 1, wherein the stop layer comprises an insulating material or a patterned conductive layer.
Regarding claim 14, Goda teaches (FIG. 2A – 2H):
A method of fabricating a memory device, comprising:
forming a stacked structure on a first surface of a stop layer, wherein the stacked structure comprises a plurality of intermediate layers and a plurality of insulating layers stacked alternately (106/108);
replacing portions of the intermediate layers with a plurality of conductive layers ([0029]);
forming a plurality of channel pillar structures extending through the stacked structure, wherein forming each channel pillar structure comprises:
forming a channel pillar extending through the stacked structure and the stop layer (118/119);
forming an insulating pillar in an inner surface of the channel pillar (130);
forming a first channel plug at a first end of the channel pillar (122);
removing a portion of the insulating pillar at a second end of each channel pillar to form a recess (FIG. 2E); and
forming a second channel plug (124) in the recess at the second end of each channel pillar; and
forming charge storage structures on outer surfaces of the channel pillar structures ([0033]).
Goda is silent regarding any bank edges and wherein after the replacing of the portions of the intermediate layers with the plurality of conductive layers, in the stacked structure, sidewalls of the insulating layers are protruded from sidewalls of the conductive layers.
However, Lu et al. (US 2019/0081069) teaches bank separating areas with conductive plugs (FIG. 4C, 424) and which have insulating layers 412 which protrude from and provide isolation from the plug for conductive layers 410.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include the isolating edge of bank structures of Lu in the device of Goda for the predictable advantage of enabling a conductive plug through the stack without shorting adjacent conductive layers unintentionally.
Regarding claim 15, Goda teaches using conventional doped semiconductor materials and processes for forming the second conductive plug material, but fails to expressly disclose:
The method according to claim 14, further comprising: performing an ion implantation process to implant dopants into the second channel plug; and performing an annealing process to activate the dopants.
However, it would have been an obvious matter of design choice to one having ordinary skill in the art before the effective filing date of the claimed invention to form the doped semiconductor based plug of Goda using conventional implantation and activation processes, since applicant has not disclosed that an implantation and activation process solves any stated problem or is for any particular purpose and it appears that the invention would perform equally as well with codeposited dopant processes or any other conventional doped semiconductor deposition process.
Regarding claim 16, Goda teaches upper and lower interconnect structures but is primarily directed to the channel plug structures and fails to expressly disclose:
The method according to claim 14, further comprising: forming a first portion of a first interconnect structure over a first substrate; forming a first portion of a bonding structure over the first portion of the first interconnect structure; forming a second portion of the first interconnect structure over the stacked structure and connected to the first channel plug; forming a second portion of the bonding structure over the second portion of the first interconnect structure; and bonding the first portion of the bonding structure to the second portion of the bonding structure.
However, Lu teaches a stacked memory structure wherein a lower interconnect structure is formed on a first substrate and a memory stack is formed on a second substrate including sacrificial intermediate layers, etch stop layers, interconnect structures, and channel plugs. The memory structure is then bonded to the lower interconnect structure and a top interconnect structure is formed (FIG. 3A – 5C and associated text).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory structure of Goda using the temporary carrier process of Lu for the predictable advantage of enabling effective processing of array and periphery devices without adversely impacting each other (Lu [0050]).
Regarding claim 17, Goda teaches upper and lower interconnect structures but is primarily directed to the channel plug structures and fails to expressly disclose:
The method according to claim 16, further comprising: forming the stop layer on a second substrate; removing the second substrate, and exposing the second end of each channel pillar; and forming a second interconnect structure over a second surface of the stop layer and connected to the second channel plug, wherein a bottom surface of the second channel plug is closer to the first substrate than the first surface of the stop layer.
However, Lu teaches a stacked memory structure wherein a lower interconnect structure is formed on a first substrate and a memory stack is formed on a second substrate including sacrificial intermediate layers, etch stop layers, interconnect structures, and channel plugs. The memory structure is then bonded to the lower interconnect structure and a top interconnect structure is formed (FIG. 3A – 5C and associated text).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory structure of Goda using the temporary carrier process of Lu for the predictable advantage of enabling effective processing of array and periphery devices without adversely impacting each other (Lu [0050]).
Regarding claim 18, Goda teaches upper and lower interconnect structures but is primarily directed to the channel plug structures and fails to expressly disclose:
The method according to claim 17, wherein a method of forming the second channel plug of each channel pillar structure comprises: forming a channel material on the second surface of the stop layer and in the recess; and removing the channel material on the second surface of the stop layer to form the second channel plug in the recess.
Regarding claim 19, Goda teaches upper and lower interconnect structures but is primarily directed to the channel plug structures and fails to expressly disclose:
The method according to claim 18, wherein forming the second interconnect structure comprises forming a conductive pad or a via connected to the second channel plug.
However, Lu teaches a stacked memory structure wherein a lower interconnect structure is formed on a first substrate and a memory stack is formed on a second substrate including sacrificial intermediate layers, etch stop layers, interconnect structures, and channel plugs. The memory structure is then bonded to the lower interconnect structure and a top interconnect structure is formed (FIG. 3A – 5C and associated text).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory structure of Goda using the temporary carrier process of Lu for the predictable advantage of enabling effective processing of array and periphery devices without adversely impacting each other (Lu [0050]).
Regarding claim 20, Goda teaches upper and lower interconnect structures but is primarily directed to the channel plug structures and fails to expressly disclose:
The method according to claim 17, wherein a method of forming the second channel plug in the recess of each channel pillar structure comprises: forming a channel material on the second surface of the stop layer and in the recess; and patterning the channel material on the second surface of the stop layer to form a semiconductor layer, and forming the second channel plug in the recess.
However, Lu teaches a stacked memory structure wherein a lower interconnect structure is formed on a first substrate and a memory stack is formed on a second substrate including sacrificial intermediate layers, etch stop layers, interconnect structures, and channel plugs. The memory structure is then bonded to the lower interconnect structure and a top interconnect structure is formed (FIG. 3A – 5C and associated text).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to form the memory structure of Goda using the temporary carrier process of Lu for the predictable advantage of enabling effective processing of array and periphery devices without adversely impacting each other (Lu [0050]).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jerry O'Connor can be reached at (571) 272-6787. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/CORY W ESKRIDGE/Primary Examiner, Art Unit 3624