Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) presented have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 10-11 and 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over Kuo et al. [US PGPUB 20220376167] in view of Chen et al. [US PPGUB 20230061143] (hereinafter Kuo and Chen).
Regarding claim 1, Kuo teaches a semiconductor device comprising:
a substrate (10, Para 22) including a cell region, a peripheral region, and a boundary region therebetween (see annotated Fig. 1);
a lower insulating layer (30, Para 23) on the cell region and extending onto the boundary region and the peripheral region (Fig. 1);
a cell insulating layer (61, Para 25) on the lower insulating layer on the cell region (Fig. 1);
data storage patterns (50A, Para 29) in the cell insulating layer on the lower insulating layer (Fig. 1);
a first upper insulating layer (62, Para 31) on the cell insulating layer (Fig. 1);
a peripheral insulating layer (63, Para 31) on the lower insulating layer on the peripheral region (Fig. 1); and
peripheral conductive line (74B, Para 33) in the peripheral insulating layer on the lower insulating layer (Fig. 1),
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region (Fig. 1), wherein a side of the peripheral insulating layer is in contact both with a side surface of the cell insulating layer and a side surface of the first upper insulating layer (Fig. 1), and
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (wherein peripheral insulating layer is ultra-low dielectric constant (ULK) dielectric layer (Para 23) and cell insulating layer silicon nitride (Para 25)),
wherein the peripheral insulating layer has a stepped structure on the boundary region (Fig. 1).
Kuo does not specifically disclose plurality of peripheral conductive lines.
Referring to the invention of Chen, Chen discloses a detailed plan view of a memory device (Fig. 1/2), wherein in the peripheral region 154, plurality of peripheral conductive lines 142d are provided (Fig. 1/2).
In view of such teaching by Chen, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Kuo comprise plurality of peripheral conductive lines in the peripheral region as disclosed by Chen at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C), wherein such implementation can improve logic signal timing due to plurality of signal paths.
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Annotated Fig. 1
Regarding claim 10, Kuo teaches a semiconductor device wherein the lower insulating layer on the cell region comprises an upper surface that is recessed toward the substrate and is between the data storage patterns (Fig. 1; i.e., uneven surface of 30 in regions d between metal structure 42), and
wherein an upper surface of the lower insulating layer on the peripheral region is lower than the recessed upper surface of the lower insulating layer on the cell region relative to the substrate (Fig. 1).
Regarding claim 11, the modified invention of Kuo teaches a semiconductor device further comprising:
lower electrode contacts (42, Kuo, Para 21) passing through the lower insulating layer on the cell region and connected to the data storage patterns, respectively (Fig. 1); and
peripheral conductive contacts (74A, Kuo, Para 24, Fig. 1 –where the plurality of peripheral conductive contacts is made obvious in view of Chen’s structure where the peripheral conductive lines 142d are connected to peripheral conductive contacts 152a, Chen, Fig. 1) connected to the peripheral conductive lines, respectively (Kuo/Chen, Fig. 1), and passing through the lower insulating layer and a lower portion of the peripheral insulating layer on the peripheral region (Kuo, Fig. 1).
Regarding claim 13, Kuo teaches a semiconductor device comprising:
a substrate (10, Para 22) including a cell region, a peripheral region, and a boundary region therebetween (see annotated Fig. 1);
a lower insulating layer (30, Para 23) on the cell region and extending onto the boundary region and the peripheral region (Fig. 1);
a cell insulating layer (61, Para 25) on the lower insulating layer on the cell region (Fig. 1);
a first upper insulating layer (62, Para 31) on the cell insulating layer (Fig. 1);
data storage patterns (50A, Para 29) in the cell insulating layer on the lower insulating layer (Fig. 1);
a peripheral insulating layer (63, Para 31) on the lower insulating layer on the peripheral region (Fig. 1); and
peripheral conductive line (74B, Para 33) in the peripheral insulating layer on the lower insulating layer (Fig. 1),
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (wherein peripheral insulating layer is ultra-low dielectric constant (ULK) dielectric layer (Para 23) and cell insulating layer silicon nitride (Para 25)),
wherein a side of the peripheral insulating layer is in contact both with a side surface of the cell insulating layer and a side surface of the first upper insulating layer (Fig. 1), and
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region (Fig. 1) and has a stepped structure on the boundary region (Fig. 1).
Kuo does not specifically disclose plurality of peripheral conductive lines.
Referring to the invention of Chen, Chen discloses a detailed plan view of a memory device (Fig. 1/2), wherein in the peripheral region 154, plurality of peripheral conductive lines 142d are provided (Fig. 1/2).
In view of such teaching by Chen, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Kuo comprise plurality of peripheral conductive lines in the peripheral region as disclosed by Chen at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C), wherein such implementation can improve logic signal timing due to plurality of signal paths.
Regarding claim 14, Kuo teaches a semiconductor device wherein an uppermost surface of the peripheral insulating layer on the boundary region is higher than an upper surface of the peripheral insulating layer on the peripheral region relative to the substrate (see annotated Fig. 1).
Claims 1-2, 5-8, 13 and 21-22 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. [US PGPUB 20220310902] in view of Chen (hereinafter Wang).
Regarding claim 1, Wang teaches a semiconductor device comprising:
a substrate (10, Para 22) including a cell region, a peripheral region, and a boundary region therebetween (see annotated Fig. 1);
a lower insulating layer (102, Para 17) on the cell region and extending onto the boundary region and the peripheral region (Fig. 5);
a cell insulating layer (118, Para 21) on the lower insulating layer on the cell region (Fig. 1/5);
data storage patterns (112, Para 18) in the cell insulating layer on the lower insulating layer (Fig. 1/5);
a first upper insulating layer (124, Para 29 or 124/126, Para 29 (an interpretation due to the limitations of claims 5-8)) on the cell insulating layer (Fig. 5);
a peripheral insulating layer (122, Para 28) on the lower insulating layer on the peripheral region (Fig. 5); and
peripheral conductive line (M3, Para 28) in the peripheral insulating layer on the lower insulating layer (Fig. 5),
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region (Fig. 5), wherein a side of the peripheral insulating layer is in contact both with a side surface of the cell insulating layer and a side surface of the first upper insulating layer (Fig. 5), and
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (wherein peripheral insulating layer is SiCN (Para 29) and cell insulating layer silicon nitride (Para 21)),
wherein the peripheral insulating layer has a stepped structure on the boundary region (Fig. 5).
Wang does not specifically disclose plurality of peripheral conductive lines.
Referring to the invention of Chen, Chen discloses a detailed plan view of a memory device (Fig. 1/2), wherein in the peripheral region 154, plurality of peripheral conductive lines 142d are provided (Fig. 1/2).
In view of such teaching by Chen, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Wang comprise plurality of peripheral conductive lines in the peripheral region as disclosed by Chen at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C), wherein such implementation can improve logic signal timing due to plurality of signal paths.
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Annotated Fig. 5
Regarding claim 2, Wang teaches a semiconductor device wherein an upper surface of the peripheral insulating layer on the peripheral region is lower than an upper surface of the first upper insulating layer relative to the substrate (Fig.5).
Regarding claim 5, Wang teaches a semiconductor device further comprising cell conductive lines (114/V3/M4, Para 18/29) passing through the first upper insulating layer and an upper portion of the cell insulating layer to be connected to the data storage patterns (Fig. 5),
wherein upper surfaces of the peripheral conductive lines are lower than upper surfaces of the cell conductive lines relative to the substrate (Fig. 5).
Regarding claim 6, Wang teaches a semiconductor device wherein the upper surfaces of the peripheral conductive lines and the upper surface of the peripheral insulating layer on the peripheral region are at an equal height from the substrate (Fig. 5).
Regarding claim 7, Wang teaches a semiconductor device wherein the upper surfaces of the cell conductive lines and the upper surface of the first upper insulating layer are at an equal height from the substrate (Fig. 5).
Regarding claim 8, Wang teaches a semiconductor further comprising an upper layer (128, Para 29) on the first upper insulating layer (Fig. 5),
wherein the upper surfaces of the cell conductive lines are free of the first upper insulating layer (Fig. 5), and
wherein the upper layer extends from the upper surface of the first upper insulating layer onto the upper surfaces of the cell conductive lines to be in contact with the upper surfaces of the cell conductive lines (Fig. 5).
Wang does not specifically disclose that the upper layer is the upper layer is an insulating layer.
However, it is noted that Wang refers to the upper layer as another stop layer (Para 29). Thus, person having ordinary skills will understand or find it obvious that layer 128 is similar the other stop layers discussed by Wang (where wang disclose stop layers 102 & 124 is an insulating layer (Para 17/29)). In view of such teaching, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have upper layer 128 being an insulating layer at least based on the rationale of relying on teachings, suggestions, or motivation in the prior art that would have led one of ordinary skill to modify the prior art reference or to combine prior art reference teachings to arrive at the claimed invention (MPEP 2143.I.G).
Regarding claim 13, Wang teaches a semiconductor device comprising:
a substrate (10, Para 22) including a cell region, a peripheral region, and a boundary region therebetween (see annotated Fig. 1);
a lower insulating layer (102, Para 17) on the cell region and extending onto the boundary region and the peripheral region (Fig. 5);
a cell insulating layer (118, Para 21) on the lower insulating layer on the cell region (Fig. 1/5);
a first upper insulating layer (124, Para 29) on the cell insulating layer (Fig. 5);
data storage patterns (112, Para 18) in the cell insulating layer on the lower insulating layer (Fig. 1/5);
a peripheral insulating layer (122, Para 28) on the lower insulating layer on the peripheral region (Fig. 5); and
peripheral conductive lines (M3, Para 28) in the peripheral insulating layer on the lower insulating layer (Fig. 5),
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (wherein peripheral insulating layer is SiCN (Para 29) and cell insulating layer silicon nitride (Para 21)), wherein a side of the peripheral insulating layer is in contact both with a side surface of the cell insulating layer and a side surface of the first upper insulating layer (Fig. 5), and
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region and has a stepped structure on the boundary region (Fig. 5).
Wang does not specifically disclose plurality of peripheral conductive lines.
Referring to the invention of Chen, Chen discloses a detailed plan view of a memory device (Fig. 1/2), wherein in the peripheral region 154, plurality of peripheral conductive lines 142d are provided (Fig. 1/2).
In view of such teaching by Chen, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Wang comprise plurality of peripheral conductive lines in the peripheral region as disclosed by Chen at least based on the rationale of using known technique to improve similar devices (methods, or products) in the same way using (MPEP 2143.I.C), wherein such implementation can improve logic signal timing due to plurality of signal paths.
Regarding claim 21, Wang teaches a semiconductor device wherein the first upper insulating layer is made of SiCN (Para 29).
Regarding claim 22, Wang teaches a semiconductor device wherein the first upper insulating layer is made of SiCN (Para 29).
Allowable Subject Matter
Claims 3, 9, 12, and 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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