Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 and 10-12 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Peng et al. [US PGPUB 20200106007] (hereinafter Peng).
Regarding claim 1, Peng teaches a semiconductor device comprising:
a substrate (semiconductor substrate, Para 19) including a cell region (CR, Fig. 2), a peripheral region (LR, Fig. 2), and a boundary region (RR, Fig. 2) therebetween;
a lower insulating layer (120/130, Para 21/22) on the cell region and extending onto the boundary region and the peripheral region (Fig. 2);
a cell insulating layer (210, Para 54) on the lower insulating layer on the cell region (Fig. 2);
data storage patterns (180/182, Para 29/47) in the cell insulating layer on the lower insulating layer (Fig. 2);
a first upper insulating layer (140’, Para 56) on the cell insulating layer (Fig. 2; i.e., on bottom and side surface);
a peripheral insulating layer (220, Para 58) on the lower insulating layer on the peripheral region (Fig. 2); and
peripheral conductive lines (234, Para 61) in the peripheral insulating layer on the lower insulating layer (Fig. 2),
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region to be in contact with a side surface of the cell insulating layer and a side surface of the first upper insulating layer (Fig. 2), and
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (Para 59).
Regarding claim 10, Peng teaches a semiconductor device wherein the lower insulating layer on the cell region comprises an upper surface that is recessed toward the substrate (Fig. 2, i.e., surface of layer 130 contacting layer 140’) and is between the data storage patterns (Fig. i.e., viewed top-to-down direction), and
wherein an upper surface of the lower insulating layer on the peripheral region is lower than the recessed upper surface of the lower insulating layer on the cell region relative to the substrate (Fig. 2).
Regarding claim 11, Peng teaches a semiconductor device further comprising:
lower electrode contacts (150, Para 24-25) passing through the lower insulating layer on the cell region and connected to the data storage patterns, respectively (Fig. 2); and
peripheral conductive contacts (232, Para 61) connected to the peripheral conductive lines, respectively (Fig. 2), and passing through the lower insulating layer and a lower portion of the peripheral insulating layer on the peripheral region (Fig.2).
Regarding claim 12, Peng teaches a semiconductor device further comprising a wiring structure (110, Fig. 2, Para 20) between the substrate and the lower electrode contacts and between the substrate and the peripheral conductive contacts (Fig. 2, in view of the knowledge that the semiconductor substrate of the device has transistors and one or more metal/dielectric layers 110 over the transistors (Para 19)), and
wherein the wiring structure includes wiring lines (114, Para 20) vertically spaced apart from the substrate (Fig. 2), and wherein the lower electrode contacts and the peripheral conductive contacts are electrically connected to the wiring lines, respectively (Fig. 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 10 and 13-18 are rejected under 35 U.S.C. 103 as being unpatentable over Dutta et al. [US PGPUB 20210305494] in view of Peng (hereinafter Dutta).
Regarding claim 1, Dutta teaches a semiconductor device comprising:
a substrate (102, Para 34, Fig. 1/6) including a cell region (107, Fig. 6), a peripheral region (103, Fig. 6), and a boundary region (105, Fig. 6) therebetween;
a lower insulating layer (128, Para 47/54) on the cell region and extending onto the boundary region and the peripheral region (Fig. 6);
a cell insulating layer (138, Para 57) on the lower insulating layer on the cell region (Fig. 6);
data storage pattern (132, Para 54) in the cell insulating layer on the lower insulating layer (Fig. 6);
a first upper insulating layer (148, Para 61) on the cell insulating layer (Fig. 6);
a peripheral insulating layer (42, Para 59) on the lower insulating layer on the peripheral region (Fig. 6); and
peripheral conductive lines (144-1/146, Para 59) in the peripheral insulating layer on the lower insulating layer (Fig. 6),
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region to be in contact with a side surface of the cell insulating layer and a side surface of the first upper insulating layer (Fig. 6; i.e. sidewall surface of the cell insulating layer and bottom side surface of the first upper insulating layer), and
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (Para 57/58).
Dutta does not specifically disclose data storage patterns.
Referring to the invention of Peng, Peng discloses a semiconductor device comprising data storage patterns (180/182, Para 29/47) in the cell region of the device (Fig. 2).
In view of such teaching by Peng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Dutta comprise the teachings of Peng in order to increase the memory capacity of the device.
Regarding claim 2, Dutta teaches a semiconductor device wherein an upper surface of the peripheral insulating layer on the peripheral region is lower than an upper surface of the first upper insulating layer relative to the substrate (Fig. 6).
Regarding claim 3, Dutta teaches a semiconductor device wherein an uppermost surface of the peripheral insulating layer on the boundary region is higher than the upper surface of the peripheral insulating layer on the peripheral region relative to the substrate (Fig. 6).
Regarding claim 4, Dutta teaches a semiconductor device wherein the peripheral insulating layer has a stepped structure on the boundary region (Fig. 6).
Regarding claim 5, Dutta in view of Peng teaches a semiconductor device further comprising cell conductive lines (134, Dutta, Para 54, where Peng teaches pluralities of data storage pattern and each have a cell conductive lines) passing an upper portion of the cell insulating layer to be connected to the data storage patterns (Dutta, Fig. 6).
The modified invention of Dutta in view of Peng does not specifically disclose that cell conductive lines 134 passing through the first upper insulating layer; and
wherein upper surfaces of the peripheral conductive lines are lower than upper surfaces of the cell conductive lines relative to the substrate.
Referring to Fig. 2 of Peng’s invention, Peng teaches a semiconductor device further comprising cell conductive lines (252, Para 60) passing through upper insulating layer (240, Para 60) and an upper portion of the cell insulating layer to be connected to the data storage patterns.
In view of such teaching by Peng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention of Dutta further comprise the teachings of Peng to allow for input or output signal(s) being sent to the MTJ of the device.
In view of such teaching by Peng, a person having ordinary skills in the art will find the limitation of claim 5 being met. That is, Dutta’s invention will have, a conductive line passing through the first upper insulating layer 148 (as suggested by Peng; where the conductive line passing through the first upper insulating layer 148 and electrode 134 serve as the cell conductive lines in Dutta’s device), and as such would result in upper surfaces of the peripheral conductive lines being lower than upper surfaces of the cell conductive lines relative to the substrate.
Regarding claim 6, the modified invention of Dutta discloses the limitation of claim 5 upon which in depends.
The modified invention does not specifically disclose wherein the upper surfaces of the peripheral conductive lines and the upper surface of the peripheral insulating layer on the peripheral region are at an equal height from the substrate.
Referring further to Peng’s invention, Peng teaches forming plurality of peripheral conductive lines (230, Para 61, Fig. 2) and the upper surface of peripheral insulating layer (220, Para 61) on peripheral region (LR, Fig. 2) are at an equal height from the substrate of the device.
In view of such teaching by Peng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Dutta comprise the teachings of Peng in order to improve electrical connectivity and wherein the layers being at same height allows for easier deposition process.
Regarding claim 10, Dutta teaches in view of Peng a semiconductor device wherein the lower insulating layer on the cell region comprises an upper surface that is recessed toward the substrate (Dutta, Fig. 6) and is between the data storage patterns (in view of multiple data storage patterns taught by Peng), and
wherein an upper surface of the lower insulating layer on the peripheral region is lower than the recessed upper surface of the lower insulating layer on the cell region relative to the substrate (Fig. 6).
Regarding claim 13, Dutta teaches a semiconductor device comprising: a substrate (102, Para 34, Fig. 1/6) including a cell region (107, Fig. 6), a peripheral region (103, Fig. 6), and a boundary region (105, Fig. 6) therebetween;
a lower insulating layer (128, Para 47/54) on the cell region and extending onto the boundary region and the peripheral region (Fig. 6);
a cell insulating layer (138, Para 57) on the lower insulating layer on the cell region (Fig. 6);
data storage pattern (132, Para 54) in the cell insulating layer on the lower insulating layer (Fig. 6);
a peripheral insulating layer (142, Para 59) on the lower insulating layer on the peripheral region (Fig. 6); and
peripheral conductive lines (144-1/144-2/146, Para 59) in the peripheral insulating layer on the lower insulating layer (Fig. 6),
wherein the peripheral insulating layer includes a material different from a material of the cell insulating layer (Para 57/58), and
wherein the peripheral insulating layer extends onto the lower insulating layer on the boundary region and has a stepped structure on the boundary region (Fig. 6).
Dutta does not specifically disclose data storage patterns.
Referring to the invention of Peng, Peng discloses a semiconductor device comprising data storage patterns (180/182, Para 29/47) in the cell region of the device (Fig. 2).
In view of such teaching by Peng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Dutta comprise the teachings of Peng in order to increase the memory capacity of the device.
Regarding claim 14, Dutta teaches a semiconductor device wherein an uppermost surface of the peripheral insulating layer on the boundary region is higher than an upper surface of the peripheral insulating layer on the peripheral region relative to the substrate (Fig. 6).
Regarding claim 15, Dutta teaches a semiconductor device further comprising a first upper insulating layer (148, Para 61) on the cell insulating layer (Fig. 6),
wherein the peripheral insulating layer is in contact with a side surface of the first upper insulating layer (Fig. 6; i.e., surface of 142 contacting material 148 between material 144-1 and 144-2).
Regarding claim 16, Dutta teaches a semiconductor device wherein an upper surface of the first upper insulating layer is higher than the upper surface of the peripheral insulating layer on the peripheral region relative to the substrate (Fig. 6).
Regarding claim 17, Dutta teaches a semiconductor device further comprising:
a first upper insulating layer (148, Para 61) on the cell insulating layer (Fig. 6); and
cell conductive lines (134, Dutta, Para 54, where Peng teaches pluralities of data storage pattern and each have a cell conductive lines) passing through an upper portion of the cell insulating layer to be connected to the data storage patterns (Fig. 6),
wherein upper surfaces of the peripheral conductive lines are free of the peripheral insulating layer (Fig. 6).
The modified invention of Dutta in view of Peng does not specifically disclose that cell conductive lines 134 passing through the first upper insulating layer; and
wherein upper surfaces of the peripheral conductive lines are lower than upper surfaces of the cell conductive lines relative to the substrate.
Referring to Fig. 2 of Peng’s invention, Peng teaches a semiconductor device further comprising cell conductive lines (252, Para 60) passing through upper insulating layer (240, Para 60) and an upper portion of the cell insulating layer to be connected to the data storage patterns.
In view of such teaching by Peng, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the modified invention of Dutta further comprise the teachings of Peng to allow for input or output signal(s) being sent to the MTJ of the device.
In view of such teaching by Peng, a person having ordinary skills in the art will find the limitation of claim 5 being met. That is, Dutta’s invention will have, a conductive line passing through the first upper insulating layer 148 (as suggested by Peng; where the conductive line passing through the first upper insulating layer 148 and electrode 134 serve as the cell conductive lines in Dutta’s device), and as such would result in upper surfaces of the peripheral conductive lines being lower than upper surfaces of the cell conductive lines relative to the substrate.
Regarding claim 18, Dutta teaches in view of Peng a semiconductor device wherein the lower insulating layer on the cell region comprises an upper surface that is recessed toward the substrate (Dutta, Fig. 6) and is between the data storage patterns (in view of multiple data storage patterns taught by Peng), and
wherein an upper surface of the lower insulating layer on the peripheral region is lower than the recessed upper surface of the lower insulating layer on the cell region relative to the substrate (Fig. 6).
Allowable Subject Matter
Claims 7-9 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/ISMAIL A MUSE/Primary Examiner, Art Unit 2812