DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 3, 8 – 16, 18, 25 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Kyogoku et al. (US 10,199,466) in view of Fujiwara et al. (JP 2014-207326).
(Claim 1) Kyogoku et al. teach a method of forming a semiconductor device, the method comprising:
providing a semiconductor layer structure (fig. 5 #10);
etching a first gate trench (fig. 5 #49, #59) into the semiconductor layer structure at a first level therein (fig. 6 #51b, 61b);
etching a second gate trench (fig. 6 #50, 60) into the semiconductor layer structure to a second level therein (bottoms 53, 63);
wherein etching the second gate trench (fig. 6) is performed after etching the first gate trench (fig. 5), and
performing an ion implantation (fig. 7 #Al, 132a, 132b) into a bottom surface (53, 63) of the second gate trench and into at least a portion of one sidewall (52, 62) of the second gate trench that extends from a top of the semiconductor layer structure,
wherein after performing the ion implantation at least one corner of the first gate trench at the first level (left corner, junction of side 51a and bottom 51b) is free of the ion implantation (fig. 7 #132a, col. 18 lines 25 — 31),
wherein the second gate trench (fig. 6 #50, 60) is deeper (bottom 53, 63) than the first gate trench (49, 59 with bottoms at 51b, 61b), and
wherein at least a portion of the second gate trench (fig. 6 #61C) is connected to the first gate trench.
Kyogoku et al. lack wherein, after etching the second gate trench, at least a portion of the first gate trench is at the first level.
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However, Fujiwara et al. teach wherein, after etching the second gate trench, at least a portion of the first gate trench is at the first level (fig. 3D) for the benefit of maintaining a flat bottom surface with constant electric field.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of maintain a constant electric filed at the bottom of the trenches.
(Claim 2) Kyogoku et al. lack wherein etching the second gate trench is preceded by forming a mask on at least a portion of the first gate trench.
However, Fujiwara et al. teach wherein etching the second gate trench is preceded by forming a mask (fig. 3b #17) on at least a portion of the first gate trench for the benefit of preventing etching the first opening (5) at the corners.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of preventing etching the first opening at the corners.
(Claim 3) Kyogoku et al. teach the method further comprising:
forming a gate insulating layer (fig. 10 #116a, #216a) on the first gate trench and the second gate trench; and
forming a gate electrode (fig. 11 #18a) on the gate insulating layer.
(Claim 8) Kyogoku et al. teach wherein performing the ion implantation into the bottom surface of the second gate trench comprises performing an angled ion implant (fig. 7 #132a, col. 18 lines 25 — 31, oblique); and
wherein the at least one corner of the first gate trench at the first level is free of the angled ion implant (fig. 7 left corner) and is adjacent a channel of the semiconductor device ((fig. 11 interface of 28a/16a, col. 6 lines 44 – 60).
(Claim 9) Kyogoku et al. teach wherein the semiconductor layer (fig. 7 #10) structure comprises a drift region (26) having a first conductivity type (N) and a well region (28) having a second conductivity type (P), and
wherein performing the ion implantation into the bottom surface of the second gate trench comprises performing the ion implantation of a deep shielding pattern (132a) having the second conductivity type (P+) into a sidewall and the bottom surface of the second gate trench.
(Claim 10) Kyogoku et al. teach wherein the deep shielding pattern (fig. 7 #132a) extends to contact at least a portion of the well region (28b).
(Claim 11) Kyogoku et al. teach a method of forming a semiconductor device, the method comprising:
providing a semiconductor layer structure (fig. 4); and
forming a gate trench(fig. 11 #50) in the semiconductor layer structure, wherein forming the gate trench comprises:
etching a first gate trench (fig. 5 #49, 59) into the semiconductor layer structure to a first level therein (fig. 6 #51b, 61b); and
after etching the first gate trench to the first level, etching a second gate trench (fig. 6 #50, 60) into the semiconductor layer structure to a second level (53, 63) therein that is different from the first level (516, 61b),
wherein after etching the second gate trench, the gate trench has a bottom surface (fig. 6 #51b, 61b) comprising a first portion at the first level (51b, 61b) of the first gate trench (49, 59) and a second portion (53, 63) at the second level (53, 63) of the second gate trench (50, 60), different from the first level (51b, 61b), and
further comprises first (51/51a, 61a/61b) and second sidewalls (52, 62) that extend from a top of the gate trench to the first (51b, 61b) and second levels (53, 63), respectively,
wherein the first sidewall comprises a channel of the semiconductor device (fig. 11 interface of 28a/16a, col. 6 lines 44 – 60).
Kyogoku et al. lack wherein, after etching the second gate trench, at least a portion of the first gate trench is at the first level such that the gate trench has a bottom surface comprising a first portion at the first level of the first gate trench and a second portion at the second level of the second gate trench.
However, Fujiwara et al. teach wherein, after etching the second gate trench, at least a portion of the first gate trench is at the first level such that the gate trench has a bottom surface comprising a first portion at the first level of the first gate trench and a second portion at the second level of the second gate trench (fig. 3D) for the benefit of maintaining a flat bottom surface with constant electric field.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of maintain a constant electric filed at the bottom of the trenches.
(Claim 12) Kyogoku et al. teach wherein the semiconductor layer structure (fig. 6) comprises a substrate (24), and wherein the second level (53, 63) is closer to the substrate (24) than the first level (51b, 61b).
(Claim 13) Kyogoku et al. teach wherein the substrate (10/24) comprises silicon carbide (col. 4 line 61).
(Claim 14) Kyogoku et al. teach wherein providing the semiconductor layer structure (fig. 7) comprises:
forming a drift region (26) having a first conductivity type (N);
forming a well region (28) having a second conductivity type (P) on the drift region (26); and
forming a deep shielding pattern (132a) having the second conductivity type (P) below at least a portion of the bottom surface of the gate trench.
(Claim 15) Kyogoku et al. teach wherein the deep shielding pattern (fig. 7 #132a) extends to contact at least a portion of the well region (28b).
Claim 16) Kyogoku et al. teach wherein the gate trench further comprises a first corner (left corner) between the first sidewall (51/51a) of the gate trench and the first portion of the bottom surface (51b, 61b) of the gate trench, and a second corner (middle corner) between the first portion (51b, 61b) of the bottom surface of the gate trench and the second portion of the bottom surface (53, 63) of the gate trench.
(Claim 18) Kyogoku et al. teach wherein the deep shielding pattern (fig. 7 #132a) is between the second corner (middle corner between fig. 6 #51b and 51C) and the drift region (26).
Kyogoku et al. lack wherein the mask is on the at least one corner of the first gate trench, and at least one opposing corner of the first gate trench and the at least a portion of one sidewall of the second gate trench are free of the mask.
However, However, Fujiwara et al. teach wherein the mask fig. 3C #17) is on the at least one corner of the first gate trench, and at least one opposing corner of the first gate trench and the at least a portion of one sidewall of the second gate trench are free of the mask for the benefit of preventing etching the first opening (5)at the corners.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references for the benefit of preventing etching the first opening at the corners.
(Claim 26) Kyogoku et al. teach wherein at least a portion of the first corner (fig. 6 between #51a and 51b) of the gate trench is free of the deep shielding pattern (fig. 7 132a).
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 4 – 7, 17 and 21 – 24 are allowable, because prior art does not teach:
(Claim 4) wherein etching the second gate trench is performed before etching the first gate trench, and wherein, after etching the first gate trench at least a portion of the second gate trench is at the second level.
(Claim 17) wherein a second radius of curvature of the second corner is greater than a first radius of curvature of the first corner.
(Claim 21) processing the corner between the first gate trench and the second gate trench to increase a radius of curvature of the corner.
Response to Arguments
Applicant's arguments filed January 6, 2026 have been fully considered but they are not persuasive.
Applicant argues:
The Office Action concedes that Kyogoku does not disclose or suggest that, after etching the second gate trench, at least a portion of the first gate trench is at the first level. The Office Action thus relies on FIG. 3D of Fujiwara as disclosing these recitations, and asserts that it would be obvious to modify Kyogoku "for the benefit of maintain a constant electric field at the bottom of the trenches." Office Action, Page 4.
Applicant respectfully disagrees, because one of skill in the art would not modify
Kyogoku to maintain a portion of the first gate trench 49, 59 at the level shown in FIG. 5 based on the teachings of Fujiwara. In particular, Fujiwara teaches addressing issues with electric field concentration by providing a trench configuration in which a second trench 14 is symmetrically formed at the bottom of the first trench 5. The second trench 14 is formed by providing spacers 17 on opposing sidewalls of the first trench 5 and etching into the bottom of the first trench 5 using the spacers 17 as an etch mask, as shown in FIGS. 3B and 3C.
Reply:
Fujiwara teaches after forming a first trench, forming a spacer inside the trench to cover portions not intended to be etched during a second etch step. The second etch steps deepens the uncovered potions of the first trench to form a second trench.
Applicant argues:
Fujiwara then describes implanting "protective layer 13...immediately below the first trench part S and the second trench part 14 so as to cover the corners of the second trench part 14, thereby not only can the electric field at the corner of the trench portion 14 be relaxed, but also the electric field at the corner of the first trench portion S can be relaxed." Fujiwara, description of FIG. 1 (machine translation). Maintaining the depth of the first trench 5 when forming the second trench 14 in Fujiwara thus results in sharp corners (and associated electric field concentration), which Fujiwara addresses by forming protective layer 13 at both sharp corners of the first trench 5 adjacent the channels, to relax the electric field concentration, as shown in FIG. 1:
The process of Kyogoku intentionally alters the level of the first trench 49, 59 to provide inclined region 51b, 61b (adjacent the channel at the first side 51, 61), such that the channel is free of sharp corners that may result in electric field concentration. See Kyogoku, FIGS. 5-6. Indeed, as shown in FIG. 8 above, Kyogoku forms the electric field relaxation region 32b only at the sharper corner on the opposite side 52, 62 of the trench 49/50, 59/60 (which does not provide channels). See Kyogoku, Col.15, lines 33 – 46 (“since the channel region is not formed in the second side face 52, a decrease in the mobility of electrons can be neglected...by forming the channel region only on the first side face 51, the mobility of electrons of the MOSFE T 100 can be maximized').
As such, modifying Kyogoku to maintain the depth of the first trench 49, 59 as taught by Fujiwara (i.e., by forming spacers 17 on at least one sidewall and then etching the second trench 14) would result in sharp corners at both sides of the trench (as shown in FIG. 1 of Fujiwara; rather than inclined regions 51 b, 61b shown in FIG. 6 of Kyogoku) and thus increased electric field concentration adjacent the channel at the first side 51, 61. However, Kyogoku's selective implant to form the electric field relaxation region 32b at only at the sharper corner on the opposite side 52, 62 of the trench 49/50, 59/60 teaches away from forming Fujiwara's protective layer 13 at sharp corners at both sides of the trench 5.
That is, the proposed modification is contrary to the asymmetric trench design of
Kyogoku, which intentionally avoids providing the electric field relaxation region 32b on the side 51, 61 of the trench 49/50, 59/60 that functions as a channel.
Reply:
The reason for combing references is what the references teach as a whole.
In this case placing spacers inside portions of a trench not intended to be etched during an etching process. Applicant has not claimed rounded corners as a result of applicant’s spacer. Furthermore, rounded corners are brought about by the etch chemistry.
Applicant argues:
Accordingly, the combination of Kyogoku and Fujiwara do not disclose both "after
etching the second gate trench, at least a portion of the first gate trench is at the first level," and "at least one corner of the first gate trench at the first level is free of the ion implantation," as recited by Claim 1. Claim 1 and the claims dependent therefrom are therefore patentable for at least these reasons. Claim 11 includes similar recitations, and thus Claim 11 and the claims dependent therefrom are patentable for at least similar reasons.
Reply:
The recitation “at least one corner of the first gate trench at the first level is free of the ion implantation," is a result of angled ion implantation and not the result of the method employed in etching the trenches. See Kyogoku fig. 7 (angled ion implantation of the deep trench while the shallow side is free from ion implantation).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached on (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
April 8, 2026
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