The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
DETAILED ACTION
Applicant’s amendments and remarks filed 12/22/25 are acknowledged. Claims 1 – 7, 10, 13, 16, and 19. Claims 1 – 20 are pending.
Response to Amendments / Arguments
Applicant's amendments have obviated the previously-raised rejections under 35 USC 102 and necessitated new rejections under 35 USC 102, as detailed below.
Applicant's arguments regarding the amended claims versus the previously-raised rejections under 35 USC 103(a) have been fully considered but they are not persuasive. Furthermore, the arguments are moot in view of the new grounds of rejections, as necessitated by Applicant’s amendments.
Amended claims 1, 13, and 19:
Applicant asserts that “The optical modulator includes an encoder 12 that converts a bit value b, of a bit string data signal into a bit value B1 in a modulation input code. The bit value B1 is provided to a DAC 13, which "converts a modulation input code of a data signal from the encoder 12 into an analog signal, for example, into a voltage." (See, par. [0086]) (emphasis added). The analog signal is provided to one of a plurality of phase shifters 16A-16C.
Therefore, Akiyama teaches that a DAC 13 is configured to convert a bit value into an analog signal that is provided to one of a plurality of phase shifters.
Because Akiyamna explicitly teaches that the DAC13 generates an analog signal that is provided to one of a plurality of phase shifters 16A--16C. Akiyama does not anticipate a digital signal provided to a pair of p-n junctions” (1st and 2nd para. on p. 10 of the Remarks, Applicant’s emphasis)
The Examiner respectfully disagrees and notes the following:
(i) Applicant conflated an analog optical output (“MODULATION OUTPUT” in Figs. 15, 18, and 26) of the electro-optical modulator (DAC 13) and a digital electrical input B1,B2,B3 provided to the electro-optical modulator by an encoder 12. The electro-optical modulator 13 is an optical digital-to-analog converter (DAC) that functions according to its name and converts an digital electrical input B1,B2,B3 into an analog optical output, as explicitly shown in Fig. 6 of Akiyama and detailed by its description (para. 0091 – 0096). In fact, the table in Fig. 3 of Akiyama explicitly shows digital/binary electrical input signals as sequences of 0s and 1s.
The DAC disclosed by the instant application and recited by claim 1 operates according to the same principle: a digital electric signal is input and converted to an output analog (electro-optically converted/modulated) optical signal.
(ii) Amended claims 1, 13, and 19 each recite an optical digital-to-analog converter (DAC). According to its definition, a DAC converts a digital input to an analog output. Both the DAC of Akiyama and the DAC claimed by the instant application operate by the same principle.
(iii) Amended claim 1 recites p-n junctions which per se are generally rendered obvious (as a matter of common knowledge in the art) by the junctions/interfaces between the oppositely doped (P and N) regions 16A,16B,16C in Figs. 15 and 18 of Akiyama. Furthermore, the Examiner additionally applies another reference by Akiyama (US 2015/0277158 A1) which expressly names such interfaces as junctions.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 5 and 7 – 12 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama (US 2022/0278753 A1) in view of Akiyama (US 2015/0277158 A1, hereinafter Akiyama 2).
Regarding claim 1, Akiyama discloses (Figs. 15, 16, 18, and 26; para. 0085 – 0090 and 0164 – 0187) an optical digital-to-analog converter (DAC) 13 (“a digital analogue convertor (DAC) 13” at para. 0075), comprising (with reference to Fig. 18):
a first waveguide path 15A1 configured to receive a first optical signal (from the upper branch of a branch unit 22);
a second waveguide path 15B1 configured to receive a second optical signal (from the lower branch of the branch unit 22; “The optical waveguide 14 includes an input unit 21, a branch unit 22, a multiplexing unit 23, and an output unit 24. The input unit 21 inputs an optical signal (continuous wave (CW) light) from a light source 2. The branch unit 22 branches an optical signal from the input unit 21 to each of the arms 15. The two arms 15 are, for example, a Mach-Zehnder (MZ) interferometer including an upper arm 15A1 and a lower arm 151B, for example” at para. 0087);
a first phase shifter segment 16A interfacing with the first waveguide path 15A1 (by the upper portion of 16A) and the second waveguide path 15B1 (by the lower portion of 16A), wherein the first phase shifter segment 16A comprises a first pair of junctions (between a pair of P doped regions and a respective pair of N doped regions) respectively having a first length L1, and wherein the first pair of junctions is configured to receive a first digital input B1 (output by a first voltage conversion unit 17A as a sequence of 0s and 1s, as shown in Fig. 3; para. 0077) to selectively generate a first phase shift f1 (para. 0092 – 0094) between the first optical signal (in 15A1) and the second optical signal (in 15B1) in response to the first digital input B1;
a second phase shifter segment 16B interfacing with the first waveguide path 15A1 (by the upper portion of 16B) and the second waveguide path 15B1 (by the lower portion of 16B), wherein the second phase shifter segment 16B comprises a second pair of junctions (between a pair of P doped regions and a respective pair of N doped regions) respectively having a second length L2, and wherein the second pair of junctions is configured to receive a second digital input B2 (output by a first voltage conversion unit 17B as a sequence of 0s and 1s, as shown in Fig. 3) to selectively generate a second phase shift f2 (para. 0092 – 0094) between the first optical signal (in 15A1) and the second optical signal (in 15B1) in response to the second digital input B2; and
wherein the first digital input B1 and the second digital B2 input correspond to different bits of a digital signal B1 – B4 (as shown in Fig. 3; “The encoder 12 converts a first bit value b1 of the bit string data signal into a first bit value B1 in the modulation input code. The encoder 12 converts a second bit value b2 in the bit string data signal into a second bit value B.sub.2 in the modulation input code” at para. 0076; “The first phase shifter 16A of the upper arm 15A1 performs intensity modulation of an optical signal with the data signal of the first bit value B1 from the first voltage conversion unit 17A. Furthermore, the first phase shifter 16A of the lower arm 15B1 performs intensity modulation of an optical signal with the data signal of the first bit value B1 after the inversion from the first voltage conversion unit 17A. The second phase shifter 16B of the upper arm 15A1 performs intensity modulation of the optical signal with the data signal of the second bit value B2 from the second voltage conversion unit 17B” at para. 0099; also para. 0077).
While Akiyama generally renders obvious, as a matter of trivial/common knowledge in the art, that the junctions/interfaces between the oppositely doped (P and N) regions 16A,16B,16C in Figs. 15 and 18 are p-n junctions, Akiyama does not expressly name such interfaces as p-n junctions. However, Akiyama2 discloses (Figs. 1, 4, and 5; para. 0023 – 0074) an electro-optic converter that has essential structural features similar to those in Akiyama and comprises oppositely doped (P and N) regions 12a,13a (para. 0027 – 0030). Akiyama2 expressly names junctions of such oppositely doped (P and N) regions as p-n junctions (para. 0033, 0040, and 0070).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the junctions/interfaces between the oppositely doped (P and N) regions 16A,16B,16C in in Akiyama are p-n junctions, as generally renders obvious by Akiyama and expressly named by Akiyama2, as needed for proper operation of the device/modulator (i.e., electro-optic phase modulation in each waveguide arm, as detailed at para. 0033, 0040, and 0070 of Akiyama2).
In light of the foregoing analysis, the Akiyama – Akiyama2 combination teaches expressly or renders obvious all of the recited limitations.
Regarding claim 2, Akiyama expressly teaches (Figs. 2 and 18) a beam splitter 21,22 arranged upstream of the first (leftmost) phase shifter segment 16A and the second phase shifter segment 16B, wherein the beam splitter has a coupling ratio of 1:2 (a single input “CW light” is split into two paths; para. 0087); and
a beam combiner 23,24 disposed downstream (to the right) of the first phase shiter segment 16A and the second phase shifter segment 16B and configured to combine the first optical signal (in 15A1) and the second optical signal (in 15B1) to generate an optical output signal (“Modulation Output”) having a plurality of different optical output powers corresponding to different values the digital signal B1 – B3 (as shown in Figs. 6, 7, 9, 11, and 12; para. 0091 – 0096).
Regarding claim 3, Akiyama expressly teaches (Fig. 18) that the first phase shifter segment 16A comprises a first doped region having a first (N) type doping and a second doped region having a second (P) doping type. The Akiyama – Akiyama2 combination renders obvious (Figs. 1 and 5 of Akiyama2) that the first phase shifter segment comprises a first doped region arranged within a fin of semiconductor material 13 and having a first doping type doping (N). The opposite side has smaller fins 12a which may also be grouped, in full analogy with the first doped region. The second phase shifter segment would have the same structure and comprise a third doped region arranged within the fin of semiconductor material and having the first doping type and a fourth doped region arranged within the fin of semiconductor material and having the second doping type. The fin of semiconductor material can have a topmost surface that continuously extends between the first phase shifter segment and the second phase shifter segment (as is implemented/shaped for the bottom side of the embodiment in Fig. 1 of Akiyama2). A variety of other suitable/workable shapes would be well within ordinary skill in the art of optical waveguide modulators (which is noted as being high).
Regarding claim 4, the Akiyama – Akiyama2 combination renders obvious a variety of suitable/workable shapes of the doped region, including L shaped regions that contact one another along their maximum heights (to form a continuous connection as in Figs. 1 and 5 of Akiyama2).
Regarding claim 5, the Akiyama – Akiyama2 combination considers (e.g., Fig. 18 of Akiyama) the first pair of p-n junctions 16A comprises a first (upper) p-n junction (over 15A1) configured to receive a first digital input value B1 and a second (lower) p-n junction (over 15B1) configured to receive the first digital input value B1.
Regarding claim 7, the Akiyama – Akiyama2 combination considers (e.g., Figs. 1, 2, 5, and 6 of Akiyama2) interconnection wires 17 that are formed to establish electrical connections to the doped regions, as needed for proper operation, and covers a variety of other suitable/workable electrical layouts, including the recited one, which would be routine to a person of ordinary skill in the art of optical waveguide modulators (which is noted as being high). As seen in Figs. 1, 2, 5, and 6 of Akiyama2, some of the interconnect wires are configured to receive a voltage, while other wires are grounded. A proper/workable arrangement of relative positions/locations of the wires would be routine to a person of ordinary skill in the art.
Regarding claim 8, Akiyama expressly teaches (Fig. 18) that the optical DAC 13 further l1comprises:
a third phase shifter segment 16C in communication with the first waveguide path 15A1 and the second waveguide path 15B1 and disposed downstream (to the right) of the second phase shifter segment 16B, the third phase shifter segment 16C being configured to selectively generate a third phase shift f3 (para. 0092 – 0094) between the first optical signal (in 15A1) and the second optical signal (in 15B1) in response to a third digital input B3 (from a third voltage conversion unit 17C).
Regarding claim 9, Akiyama illustrates, by way of example but not limitation, several embodiments with different ratios of the length of the three phase shifters 16A,16B,16C (e.g., “Note that a ratio of the electrode lengths L1:L2:L3 is, for example, 20:21:22” at para. 0059; “In the optical modulator 3, a ratio of the electrode length L1 of the first phase shifter 16A, the electrode length L2 of the second phase shifter 16B, and the electrode length L.sub.3 of the third phase shifter 16C is set to, for example, L1:L2:L3 =21:34:45 so as to make the electric field intensities for the respective signal levels (1 to 8) at equal intervals” at para. 0098). Akiyama renders obvious that other L3:L2:L1 ratios can be used (e.g., 3:2:1), depending on a particular intended distribution of electric field intensities (as long as L3 > L2 > L1) and relative amplitudes of the different bits of the digital signal.
Regarding claim 10, the Akiyama – Akiyama2 combination considers that a ratio of the first length L1 to the second length L2 is determined according to a particular desired digital code (as taught by Akiyama) and, in particular, can be approximately equal to 1:2 or 2:1 (if the first and second phase shifters are renamed and become 16B and 16A respectively), as exemplified by Akiyama2 (Fig. 5; “the unit length is 250/(24−1)≈17 μm; and, from 17×2i-1 (i=1, 2, 3, 4), the operating lengths L1 to L4 of the side terminals 31A to 31D are as follows. L1 is about 17 μm; L2 is about 34 μm; L3 is about 68 μm; and L4 is about 136 μm” at para. 0067).
Regarding claim 11, Akiyama expressly teaches (Figs. 18 and 26) that the optical DAC 13 in Fig. 18 can be comprised in a more complex layout in Fig. 26 (IQ modulator) that comprises a tandem of the optical DACs 13 in Fig. 18 (the upper DAC 13A and the lower DAC 13B).
The lower DAC 13B has the same structure as that of the upper DAC 13A and comprises:
a third waveguide path 15A2 configured to receive a third optical signal (para. 0223);
a fourth waveguide path 15B2 configured to receive a fourth optical signal (para. 0223);
a third phase shifter segment (the 16A of 13B) in communication with the third waveguide path 15A2 and the fourth waveguide path 15B2, the third phase shifter segment being configured to selectively generate a third phase shift between the third optical signal and the fourth optical signal in response to a third digital input
B
1
Q
; and
a fourth phase shifter segment (the 16B of 13B) in communication with the third waveguide path 15A2 and the fourth waveguide path 15B2, the fourth phase shifter segment being configured to selectively generate a fourth phase shift between the third optical signal and the fourth optical signal in response to a fourth digital input
B
2
Q
.
Regarding claim 12, Akiyama expressly teaches (Fig. 26) that the first waveguide path 15A1 and the second waveguide path 15B1 are arranged in parallel to the third waveguide path 15A2 and the fourth waveguide path 15B2.
Claims 6, 13, 15, 17, and 18 qare rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Akiyama2, in view of Srinivasan et al (US 2021/0405499 A1), and further in view of Sobu et al (US 2022/0311534 A1).
Regarding claim 6, Akiyama teaches that the phase difference f0 between the first waveguide path 15A1 and the second waveguide path 15B1 (the two waveguides being the arms of a Mach-Zehnder interferometer) can be different from zero, e.g., 90o (Fig. 6; para. 0091 – 0094). While Akiyama does not expressly teach that such (bias) phase shift can be implemented by using different lengths of the Mach-Zehnder interferometer arms, this design choice is well known in the art. For example, Srinivasan discloses (Fig. 1; para. 0020 – 0023) a Mach-Zehnder interferometer 103 comprising two waveguide arms 107,109 that have a phase difference of 90o between them and expressly teaches that the phase difference is implemented by using a length difference/asymmetry between the two waveguide arms 107,109, the length difference/ asymmetry being due to an extension DL that gives a second (lower) waveguide path 109 a longer path length than a first (upper) waveguide path 107.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the first waveguide path in Akiyama can be configured, in accordance with the teachings of Srinivasan, to have a different (e.g., smaller) path length than the second waveguide path due to an extension DL in the second waveguide path, in order to create a non-zero phase bias phase difference f0, as intended by Akiyama.
The Akiyama – Akiyama2 – Srinivasan combination considers an extension DL in the second waveguide path to preset (in the design) a non-zero phase bias phase difference f0 (e.g., 90o) and a heater (18A1,18B1 in Fig. 18 of Akiyama) configured to heat a part of the second waveguide path to a higher temperature than the first waveguide path and thereby fine-tune the preset non-zero phase bias phase difference f0 after fabrication and during operation, e.g., to compensate for fabrication tolerances and temperature variations.
The Akiyama – Akiyama2 – Srinivasan combination renders obvious that the heater can be disposed at any location/space available along the second waveguide and, in particular, above the extension in order to minimize the space/length collectively taken up by the extension and the heater. While the Akiyama – Akiyama2 – Srinivasan combination does not illustrate such design choice, Sobu discloses (Figs. 10, 18, and 19; para. 0077 – 0079) an asymmetric Mach-Zehnder interferometer (the same type as that in Fig. 1 of Srinivasan) that comprises two waveguides of different lengths due to extensions (shaped as loops similar to the loop DL in Fig. 1 of Srinivasan), wherein the heaters H are each disposed above a corresponding extension. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the heater can be disposed above the extension, as a suitable/workable design choice that is generally rendered obvious by the Akiyama – Akiyama2 – Srinivasan combination and explicitly illustrated by Sobu.
Regarding claim 13, the teachings of Akiyama, Akiyama2, Srinivasan, and Sobu combine (see the arguments and motivation for combining, as provided above for claims 1 and 6) to teach expressly or render obvious all of the recited limitations, as detailed above for claims 1 and 6. Specifically, the Akiyama – Akiyama2 – Srinivasan – Sobu combination considers an optical digital-to-analog converter (DAC), comprising (with reference to Fig. 18 of Akiyama):
a first phase shifter segment 16A comprising a first plurality of (P and N) doped regions extending over a first length L1, the first plurality of doped regions forming a first p-n junction (in the upper portion of 16A) and a second p-n junction (in the lower portion of 16A);
a second phase shifter segment 16B comprising a second plurality of doped regions extending over a second length L2 that is different than the first length L1, the second plurality of doped regions forming a third p-n junction (in the upper portion of 16B) and a fourth p-n junction (in the lower portion of 16B);
a first (upper) waveguide path 15A1 having a first path length and extending through the first p-n junction and the third p-n junction (as seen in Fig. 18); and
a second (lower) waveguide path 15B1 having a second path length and extending through the second p-n junction and the fourth p-n junction (as seen in Fig. 18), the second path length being larger than the first path length (according to the teachings of Srinivasan, as detailed above for claim 6), wherein the first waveguide path (or the second wave path for that matter) comprises an extension (DL in Fig. 1 of Srinivasan) that gives the first waveguide path a longer path length than the second waveguide path; and a heater is disposed along the extension (generally rendered obvious by the Akiyama – Akiyama2 – Srinivasan combination and explicitly illustrated by Sobu).
Regarding claim 15, Akiyama teaches that the optical DAC 13 comprises a waveguide 15A1 extending along the first waveguide path and through the first p-n junction (in the upper portion 16A) and the third p-n junction (in the upper portion 16B). The use of a substrate of which the waveguide 15A1 is formed would be obvious.
Alternatively or additionally, the Examiner took official notice in the Office Action of 9/19/25 that it was well known in the art that integrated-optic waveguides are formed from layers disposed on a support substrate. Since Applicant has not traversed the official notice, the fact of common knowledge has become applicant admitted prior art.
Such substrate would be obvious to a person of ordinary skill in the art in order to enable support for the fabrication of an optical waveguide.
Regarding claim 17, Akiyama teaches (Fig. 18) that the first p-n junction (within the upper portion of 16A) is separated from the second p-n junction (within the lower) portion of 16A) along a first (vertical) direction and wherein the first phase shifter segment 16A is separated from the second phase shifter segment 16B along a second (horizontal) direction that is perpendicular to the first (vertical) direction.
Regarding claim 18, the Akiyama – Akiyama2 – Srinivasan – Sobu combination teaches expressly or renders obvious all of the recited limitations, as detailed above for claim 10.
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Akiyama2, in view of Srinivasan, in view of Sobu, and further in view of Sonkoly et al (US 11,164,893 B1).
Regarding claim 14, Akiyama teaches (Fig. 18) electrical connections between a voltage source 11,12 and the (P and N) doped regions, but does not detail a suitable/workable structure for them. However, Sonkoly discloses (Figs. 1 and 2; 2:28 – 3:18) an optical modulator comprising an optical waveguide 108 that can comprise a p-n junction and is modulated by a voltage provided by a signal pad (identified as 208 in Fig. 2) coupled to the first p-n junction by an interconnect structure 114,118,116 in Fig. 1).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the optical DAC of Akiyama can further comprise a plurality of signal pads that each are coupled to a respective p-n junction by a respective interconnect structure, as a suitable/workable structure that is illustrated by Sonkoly and provides electrical connections between the voltage source 11,12 and the (P and N) doped regions.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Akiyama2, in view of Srinivasan, in view of Sobu, and further in view of Li et al (US 2010/0247029 A1).
Regarding claim 16, the Akiyama – Akiyama2 – Srinivasan – Sobu combination considers a plurality of interconnects (17 in Figs. 1 and 5 of Akiyama2) and the heater (18 in Fig. 18 of Akiyama), but does not detail their relative placement. However, Li discloses (Fig. 8; para. 0063 – 0069) an electro-optic modulator 800 comprising:
a plurality of interconnects 418 arranged within a dielectric layer 416 (as identified in Fig. 7) over a substrate 410, the plurality of interconnects 418 being coupled to a p-n junction (within an optical waveguide 414; as detailed in Fig. 1 and at para. 0037); and
wherein a heater 710 is arranged vertically between the waveguide 414 and the plurality of interconnects 418-1,418-3, as shown in Fig. 8.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the plurality of interconnects and the heater of the Akiyama – Akiyama2 – Srinivasan – Sobu combination can be disposed as illustrated by Li, so that the heater is placed in a space defined by the interconnects and in proximity of the waveguide which ensures higher/improved thermo-optic efficiency.
Claims 19 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Akiyama in view of Akiyama2, and further in view of Rakowski et al (US 2022/0252910 A1).
Regarding claims 19 and 20, Akiyama teaches (Fig. 18) that the disclosed optical DAC 13 comprises p-doped and n-doped regions, but does not detail a suitable/workable method for making them. However, Rakowski discloses (Figs. 1 – 4; para. 0018 – 0023) an optical modulator comprising an optical waveguide core 12 with a p-n junction created by doped regions 28,30. Rakowski expressly teaches that the doped regions 28,30 can be formed by an implantation process.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention that the doped regions in the DAC of Akiyama can be formed by a implantation process as a suitable/workable method for forming doped regions that as expressly identified by Rakowski.
The Akiyama – Rakowski combination considers a method of forming an optical DAC, comprising:
performing a first implantation process to implant dopants with a first (e.g., N) doping type into a substrate (the top silicon layer of an SOI substrate, as taught by Rakowski; para. 0022) to form a first pair of doped regions (the pair of N-doped regions in the phase shifter 16A in Fig. 18 of Akiyama) and a second pair of doped regions (the pair of N-doped regions in the phase shifter 16B);
performing a second implantation process (with a different implantation mask) to implant dopants with a second (P) doping type into the substrate to form a third pair of doped regions (the pair of P-doped regions in the phase shifter 16A in Fig. 18 of Akiyama) and a fourth pair of doped regions (the pair of P-doped regions in the phase shifter 16B) (“The doped regions 28, 29 may be concurrently formed in the waveguide cores 12, 14 by a masked ion implantation process, and the doped regions 30, 31 may be concurrently formed in the waveguide cores 12, 14 by a separate masked ion implantation process” at para. 0019 of Rakowski), the third pair of doped regions abutting the first pair of doped regions along a first pair of PN junctions (within the phase shifter 16A) respectively having a first length L1 (as identified in Fig. 18) and the fourth pair of doped regions abutting the second pair of doped regions along a second pair of PN junctions (within the phase shifter 16B) respectively having a second length L2; and
patterning the substrate to form a first waveguide path 15A1 with a first path length and a second waveguide path 15A2 with a second path length, the first waveguide path and the second waveguide path respectively extending through one of the first pair of PN junctions and one of the second pair of PN junctions (as seen in Fig. 18).
Finally, the Akiyama – Akiyama2 – Rakowski combination renders obvious that a ratio of the first length to the second length can be approximately equal to 2:1, as detailed above for claim 10.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ROBERT TAVLYKAEV whose telephone number is (571)270-5634. The examiner can normally be reached 10:00 am - 6:00 pm, Monday - Friday.
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/ROBERT TAVLYKAEV/Primary Examiner, Art Unit 2896
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