DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 7, 9, 15-17, and 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (“Lu” US 2020/0312770) and Nam et al. (“Nam” US 2023/0178469).
Regarding claim 1, Lu discloses a semiconductor package (2, Figure 2), comprising:
an interposer (BL1) over a substrate (CL/BL2) that includes interconnect traces (the substrate Cl/BL2 includes interconnects 104B);
a redistribution structure (S1) on the interposer (BL1, see Figure 2);
a first semiconductor structure (TD12) on the redistribution structure (S1) that is disposed on the interposer (BL1, see Figure 2), wherein the first semiconductor structure (TD12) includes a first semiconductor die (TD12);
a second semiconductor structure (TD13) on the redistribution structure (S1), wherein the second semiconductor structure (TD13) includes a second semiconductor die (TD13);
conductive components (C11/C12/C13) disposed between the redistribution structure (S1) and the first semiconductor structure (TD12), the second semiconductor structure (TD13) and the third semiconductor structure (TD11, see Figure 2);
an underfill layer (E1) surrounding the conductive components (C11/C12/C13) and filling gaps between the conductive components (C11/C12/C13, see Figure 2),
a molding compound (UF1) surrounding the first semiconductor structure (TD12), the second semiconductor structure (TD13), the third semiconductor structure (TD11) and the underfill layer (E1, see Figure 2),
a third semiconductor structure (TD11) on the redistribution structure (S1) and adjacent to a corner or an edge of the substrate (CL/BL2, see Figure 3) in a top plan view of the substrate (Figure 3), wherein the third semiconductor structure (TD11) includes a third semiconductor die (TD11) and a
wherein the third semiconductor structure (TD11) is electrically insulated from the substrate (CL/BL2), the first semiconductor structure (TD12) and the second semiconductor structure (TD13, due to the dies/structures TD11, TD12, TD13, having means of electrical insulation surrounding the electrical connections therefor, see the lower surfaces of each die having electrical interconnects in Figure 2, the third semiconductor structure would be electrically insulated from the other dies through the electrical insulation material, further, the substrate comprises insulating material 106B, thus the third semiconductor die TD11 is electrically insulated from the substrate insulating material 106B, otherwise, one having ordinary skill in the art would recognize that there would be electrical shorts in the device due to the wiring of the components, substrates, RDLs, interposers, etc., being electrically insulated with insulating material).
Lu does not disclose a first encapsulant that encapsulates the first semiconductor die, a second encapsulant that encapsulates the second semiconductor die, and a third encapsulant that encapsulates the third semiconductor die, wherein the first encapsulant, the second encapsulant, and the third encapsulant are separated from each other.
Nam discloses in Figures 1 and 2B, however, a first encapsulant (610) that encapsulates the first semiconductor die (chip stack 200 at the central portion of the package), a second encapsulant (610) that encapsulates the second semiconductor die (rightmost chip stack 200 in Figure 2B), and a third encapsulant (610) that encapsulates the third semiconductor die (leftmost chip stack 200 in Figure 2B), wherein the first encapsulant, the second encapsulant, and the third encapsulant (610 on each separate semiconductor die, see Figures 1 and 2B) are separated from each other (the reference numeral 610 refers to the same chip molding or encapsulant material, yet it is clear that these different encapsulants are physically separate from each other, see Figures 1 and 2B).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Nam into the teachings of Lu to include the claimed first, second, and third encapsulants for the purpose of minimizing warpage in the semiconductor package (see para. [0079]).
The combination of Lu and Nam would result in a configuration where the underfill layer is adjacent to the third encapsulant because the third encapsulant would be located directly contacting lateral sidewalls of the third semiconductor die, thus would be adjacent to the underfill layer as well.
Regarding claim 2, Lu discloses wherein no electrical signal is transmitted between the third semiconductor structure (TD11) and any of the substrate (CL/BL2), the first semiconductor structure (TD12) and the second semiconductor structure (TD13, see para. [0030] and [0037], the third semiconductor structures is a non-operating die, a die configured for non-use, or a die without devices therein, therefore no electrical signals would be transmitted therethrough to other components of the device).
Regarding claim 3, Lu discloses wherein the second semiconductor structure (TD13) and the third semiconductor structure (TD11) are disposed at opposite sides of the first semiconductor structure (TD12, see Figures 2 and 3).
Regarding claim 4, Lu discloses wherein the third semiconductor structure (TD11) is disposed adjacent to a corner or an edge of the interposer (BL1, see Figures 2 and 3) in the top plan view of the interposer (see Figure 3).
Regarding claim 5, Lu discloses wherein the first semiconductor structure (TD12) and the second semiconductor structure (TD13) are electrically connected to the substrate (CL/BL2) by the redistribution structure (S1) and conductive pillars (vias 108A) of the interposer (BL1, see Figure 2).
Regarding claim 7, the combination of Lu and Nam discloses wherein an arrangement of the second semiconductor die (TD13) and the second encapsulant (incorporated by the chip encapsulants 610 of Nam) is identical to an arrangement of the third semiconductor die (TD11) and the third encapsulant (incorporated by the chip encapsulants 610 of Nam into the first, second, and third semiconductor structures of Lu, Nam shows the arrangement of the second and third encapsulants 610 on the second and third semiconductor dies are arranged identically, i.e. the encapsulants are located on lateral surfaces of the dies).
Regarding claim 9, the combination of Lu and Nam discloses wherein the third encapsulant (610 of Nam incorporated into the third semiconductor structure TD11 of Lu) of the third semiconductor structure (TD11) comprises a material that is the same as the second encapsulant (610 of Nam incorporated into the second semiconductor structure TD13 of Lu) of the second semiconductor structure (TD13, since the encapsulant of each semiconductor structure is the same encapsulant 610 in Nam, they are made of the same material).
Regarding claim 15, Lu discloses a semiconductor package (2, Figure 2), comprising:
a first structure (P1) and a second structure (P2) over a substrate (CL/BL2) that includes interconnect traces (104B/108B/TH, see Figure 2), and the second structure (P2) is adjacent to the first structure (P1, see Figure 2), wherein each of the first structure (P1) and the second structure (P2) comprises:
an interposer (BL1) over the substrate (CL/BL2);
a redistribution structure (S1 in the first structure, S2 in the second structure) on the interposer (BL1);
a first semiconductor structure (TD12 in the first structure, TD22 in the second structure) on the redistribution structure (S1, S2) that is disposed on the interposer (BL1), wherein the first semiconductor structure (TD12, TD22) includes a first semiconductor die (TD12, TD22);
a second semiconductor structure (TD13 in the first structure, TD23 in the second structure) on the redistribution structure (S1/S2), wherein the second semiconductor structure (TD13, TD23) includes a second semiconductor die (TD13, TD23);
a third semiconductor structure (TD11 in the first structure, TD21 in the second structure) on the redistribution structure (S1, S2), wherein the third semiconductor structure (TD11, TD21) includes a third semiconductor die (TD11, TD21), wherein the third semiconductor structure (TD11, TD21) is electrically insulated from the substrate (CL/BL2), the first semiconductor structure (TD12, TD22) and the second semiconductor structure (TD13, TD23, due to the dies/structures TD11, TD12, TD13, TD21, TD22, TD23, having means of electrical insulation surrounding the electrical connections therefor, see the lower surfaces of each die having electrical interconnects in Figure 2, the third semiconductor structure would be electrically insulated from the other dies through the electrical insulation material, further, the substrate comprises insulating material 106B, thus the third semiconductor die TD11, TD21 is electrically insulated from the substrate insulating material 106B, otherwise, one having ordinary skill in the art would recognize that there would be electrical shorts in the device due to the wiring of the components, substrates, RDLs, interposers, etc., being electrically insulated with insulating material),
conductive components (C11/C12/C13, C21/C22/C23) disposed between the redistribution structure (S1, S2) and the first semiconductor structure (TD12, TD22), the second semiconductor structure (TD13, TD23) and the third semiconductor structure (TD11, TD21, see Figure 2);
an underfill layer (E1, E2) surrounding the conductive components (C11/C12/C13, C21/C22/C23) and filling gaps between the conductive components (C11/C12/C13, C21/C22/C23, see Figure 2),
a molding compound (UF1, UF2) surrounding the first semiconductor structure (TD12, TD22), the second semiconductor structure (TD13, TD23), the third semiconductor structure (TD11, TD12) and the underfill layer (E1, E2, see Figure 2),
wherein the third semiconductor structures (TD11, TD21) of the first structure (P1) and the second structure (P2) are disposed adjacent to two corners or two edges of the substrate (CL/BL2) in a top plan view of the substrate (see Figure 3, which shows each third semiconductor structure of each structure P1/P2 are either disposed adjacent to a corner or edge of the substrate, where the synonyms to “adjacent” are “nearby” or “next to”).
Lu does not disclose a first encapsulant that encapsulates the first semiconductor die, a second encapsulant that encapsulates the second semiconductor die, and a third encapsulant that encapsulates the third semiconductor die, wherein the first encapsulant, the second encapsulant, and the third encapsulant are separated from each other.
Nam discloses in Figures 1 and 2B, however, a first encapsulant (610) that encapsulates the first semiconductor die (chip stack 200 at the central portion of the package), a second encapsulant (610) that encapsulates the second semiconductor die (rightmost chip stack 200 in Figure 2B), and a third encapsulant (610) that encapsulates the third semiconductor die (leftmost chip stack 200 in Figure 2B), wherein the first encapsulant, the second encapsulant, and the third encapsulant (610 on each separate semiconductor die, see Figures 1 and 2B) are separated from each other (the reference numeral 610 refers to the same chip molding or encapsulant material, yet it is clear that these different encapsulants are physically separate from each other, see Figures 1 and 2B).
It would have been obvious to a person having ordinary skill in the art to incorporate the teachings of Nam into the teachings of Lu to include the claimed first, second, and third encapsulants for the purpose of minimizing warpage in the semiconductor package (see para. [0079]).
The combination of Lu and Nam would result in a configuration where the underfill layer is adjacent to the third encapsulant because the third encapsulant would be located directly contacting lateral sidewalls of the third semiconductor die, thus would be adjacent to the underfill layer as well.
Regarding claim 16, Lu discloses wherein no electrical signal is transmitted from the third semiconductor structures (TD11, TD21) of the first structure (P1) and the second structure (P2) to any of the first semiconductor structures (TD12, TD22) and the second semiconductor structures (TD13, TD23) of the first structure (P1) and the second structure (P2, see again para. [0030] and [0037], the third dies of the third semiconductor structures are a non-operating die, a die configured for non-use, or a die without devices therein, therefore no electrical signals would be transmitted therethrough to other components of the device).
Regarding claim 17, Lu discloses wherein the third semiconductor structure (TD11, TD21) of each of the first structure (P1) and the second structure (P2) is disposed adjacent to a corner or an edge of the interposer (S1/S2) in the top plan view of the interposer (S1/S2, see Figure 3).
Regarding claim 19, Lu discloses wherein in each of the first structure (P1) and the second structure (P2), the second semiconductor structure (TD13, TD23) and the third semiconductor structure (TD11, TD21) are disposed at opposite sides of the first semiconductor structure (TD12, TD22, see Figure 2C).
Regarding claim 20, the combination of Lu and Nam discloses wherein in each of the first structure (P1) and the second structure (P2), an arrangement of the second semiconductor die (TD13, TD23) and the second encapsulant (incorporated by Nam’s encapsulants 610) is identical to an arrangement of the third semiconductor die (TD11, TD21) and the third encapsulant (incorporated by the chip encapsulants 610 of Nam into the first, second, and third semiconductor structures of Lu, Nam shows the arrangement of the second and third encapsulants 610 on the second and third semiconductor dies are arranged identically, i.e. the encapsulants are located on lateral surfaces of the dies).
Regarding claim 21, the combination of Lu and Nam discloses wherein in each of the first structure (P1) and the second structure P2), the third encapsulant (610 of Nam incorporated into the third semiconductor structure TD11, TD21 of Lu) comprises the same material as the second encapsulant (610 of Nam incorporated into the second semiconductor structure TD13, TD23 of Lu, since the encapsulant of each semiconductor structure is the same encapsulant 610 in Nam, they are made of the same material).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lu and Nam as applied to claim 5 above, and further in view of Lin et al. (“Lin” US 2018/0151502).
Regarding claim 6, Nam does not disclose wherein the third semiconductor die of the third semiconductor structure is grounded.
Lin discloses, however, connecting a dummy die (106) to a ground node through metal pillars (40), see para. [0052] of Lin.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin above into the teachings of Nam to include the ground connection of the third semiconductor die, the dummy die of Nam. The claimed elements were known in the prior art before the effective filing date of the present invention, and the combination of the prior art would result in the predictable result of providing ground connection for the device to improve electromagnetic shielding. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lu and Nam as applied to claim 15 above, and further in view of Lin et al. (“Lin” US 2018/0151502).
Regarding claim 18, Lu discloses wherein in each of the first structure (P1) and the second structure (P2), the first semiconductor structure (TD12, TD22) and the second semiconductor structure (TD13, TD23) are electrically connected to the substrate (CL/BL2) by the redistribution structure (S1, S2) and conductive pillars of the interposer (vias 108A of interposer BL1).
Lu does not disclose while the third semiconductor die of the third semiconductor structure is grounded.
Lin discloses, however, connecting a dummy die (106) to a ground node through metal pillars (40), see para. [0052] of Lin.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin above into the teachings of Lu to include the ground connection of the third semiconductor die of the third semiconductor structure, the dummy die of Lu. The claimed elements were known in the prior art before the effective filing date of the present invention, and the combination of the prior art would result in the predictable result of providing ground connection for the device to improve electromagnetic shielding. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Response to Arguments
Applicant’s amendments with respect to the 112(b) rejection of claim 9 have been fully considered and overcome the 112(b) rejection. The 112(b) rejection of claim 9 has been withdrawn.
Applicant’s arguments with respect to claims 1 and 15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
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