DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species 1a in the reply filed on January 19 20206 is acknowledged. The traversal is on the ground(s) that there is no serious burden on the Examiner because Species 1a and 1b are alternative ways of describing the same concept. This is not found persuasive because, while the concept and structure of Species 1a and 1b are similar (i.e., both species have a central semiconductor structure with a certain arrangement of surrounding semiconductor structures), the structure set forth by each species as claimed are not the same. The species are specific to exactly which semiconductor structures are placed on which side of the central semiconductor structure. Species 1a requires the second and third semiconductor structures to be disposed on opposite sides of the first semiconductor structure as claimed in claims 3 and 19, whereas Species 1b requires the same second and third semiconductor structures to be disposed on opposite sides of the first semiconductor structure as claimed in claims 10 and 22. These features are mutually exclusive and are distinct and independent embodiments of the semiconductor package, thus there exists a serious examination and/or search burden for the patentably distinct species. Further, Applicant has not admitted on record that these distinct and independent package structures are obvious variants or provided proof in the art that these distinct and independent package structures would be considered obvious variants. Therefore, the election of one of the disclosed package structures is required. Applicant has the right to state on the record that all the package structures identified in the disclosure are obvious variants in which case the Examiner has the right to reject all package structure variants with any one package structure in the identified species.
Claims 10-14 and 22-27 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on January 19 2026. Claims 1-9 and 15-21 are examined.
The requirement is still deemed proper and is therefore made final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 9 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the same material" in line 2. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-5, 7, and 9 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Nam et al. (“Nam” US 2023/0178469) and supported by Cheng et al. (“Cheng” US 2021/0183844).
Regarding claim 1, Nam discloses a semiconductor package (1000, Figures 1-2C), comprising:
an interposer (base layer 310/ through-electrodes 330) over a substrate (500) that includes interconnect traces (the substrate 500 includes “wiring paths” 530, see Figure 2C);
a redistribution structure (360) on the interposer (310/330, see Figure 2C);
a first semiconductor structure (400M-1/620) on the redistribution structure (360) that is disposed on the interposer (310/330), wherein the first semiconductor structure (400M-1/620) includes a first semiconductor die (400M-1) and a first encapsulant (620) that encapsulates the first semiconductor die (400M-1, see Figure 2C);
a second semiconductor structure (400CP/620) on the redistribution structure (360), wherein the second semiconductor structure (400CP/620) includes a second semiconductor die (400CP) and a second encapsulant (620) that encapsulates the second semiconductor die (400CP, see Figure 2C); and
a third semiconductor structure (400D/620) on the redistribution structure (360) and adjacent to a corner or an edge of the substrate (500, see Figure 1) in a top plan view of the substrate (500), wherein the third semiconductor structure (400D/620) includes a third semiconductor die (400D) and a third encapsulant (620) that encapsulates the third semiconductor die (400D, see Figure 2C),
wherein the third semiconductor structure (400D/620) is electrically insulated from the substrate (500), the first semiconductor structure (400M-1/620) and the second semiconductor structure (400CP/620, due to the dies 400D, 400CP, and 400M-1 having means of electrical insulation surrounding the electrical connections therefor, see the lower surfaces of each die having electrical interconnects in Figure 2C, the third semiconductor structure would be electrically insulated from the other dies through the electrical insulation material, further, the substrate comprises insulating material 510, thus the third semiconductor die 400D is electrically insulated from the substrate insulating material 510, otherwise, one having ordinary skill in the art would recognize that there would be electrical shorts in the device due to the wiring of the components, substrates, RDLs, interposers, etc., being electrically insulated with insulating material).
Note that the Examiner has construed the claimed first, second, and third encapsulants as the “package molding layer” 620 of Nam because all the claimed first, second, and third encapsulants are formed of the same material, a molding compound, see para. [0034] of the instant specification, and the “package molding layer” 620 of Nam is also made of a molding compound, see para. [0059] of Nam. Moreover, the structure of the encapsulants as claimed is the same as the structure of the package molding layer 620 of Nam.
Regarding claim 2, Nam discloses wherein no electrical signal is transmitted between the third semiconductor structure (400D/620) and any of the substrate (500), the first semiconductor structure (400M-1/620) and the second semiconductor structure (400CP/620, since the dummy die doesn’t contain any devices, see para. [0024], there would be no electrical signal transmitted between the dummy die 400D and any other parts of the device).
Regarding claim 3, Nam discloses wherein the second semiconductor structure (400CP/620) and the third semiconductor structure (400D/620) are disposed at opposite sides of the first semiconductor structure (400M-1/620, see Figure 2C and Figure 1 which shows 400D/620 and 400CP/620 disposed on opposite sides of the first semiconductor structure 400M-1/620).
Regarding claim 4, Nam discloses wherein the third semiconductor structure (400D/620) is disposed adjacent to a corner or an edge of the interposer (310/330) in the top plan view of the interposer (see Figure 1, which shows 400D placed and the lower left corner of the interposer in the plan view of Figure 1).
Regarding claim 5, Nam discloses wherein the first semiconductor structure (400M-1/620) and the second semiconductor structure (400CP/620) are electrically connected to the substrate (500) by the redistribution structure (360) and conductive pillars (330) of the interposer (310/330, see Figure 2C and para. [0031]).
Regarding claim 7, Nam discloses wherein an arrangement of the second semiconductor die (400CP) and the second encapsulant (620) is identical to an arrangement of the third semiconductor die (400D) and the third encapsulant (620, the encapsulant 620 is considered to be the first, second, and third encapsulants because the monolithic structure of the encapsulant 620 encapsulates all three semiconductor dies, see Figure 2C which shows the structure of the encapsulant over each die 400CP and 400D is identical, i.e. covers upper and lateral surfaces of the semiconductor dies).
Regarding claim 9, Nam discloses wherein the third encapsulant (620) of the third semiconductor structure (400D/620) comprises the same material as the second encapsulant (620) of the second semiconductor structure (400CP/620, since the encapsulant of each semiconductor structure is the same encapsulant, they are made of the same material).
Claims 15-17 and 19-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lu et al. (“Lu” US 2020/0312770).
Regarding claim 15, Lu discloses a semiconductor package (2, Figure 2), comprising:
a first structure (P1) and a second structure (P2) over a substrate (CL/BL2) that includes interconnect traces (104B/108B/TH, see Figure 2), and the second structure (P2) is adjacent to the first structure (P1, see Figure 2), wherein each of the first structure (P1) and the second structure (P2) comprises:
an interposer (BL1) over the substrate (CL/BL2);
a redistribution structure (S1 in the first structure, S2 in the second structure) on the interposer (BL1);
a first semiconductor structure (TD12 and E1 in the first structure, TD22 and E2 in the second structure) on the redistribution structure (S1, S2) that is disposed on the interposer (BL1), wherein the first semiconductor structure (TD12/E1, TD22/E2) includes a first semiconductor die (TD12, TD22) and a first encapsulant (E1, E2) that encapsulates the first semiconductor die (TD12, TD22, see Figure 2);
a second semiconductor structure (TD13 and E1 in the first structure, TD23 and E2 in the second structure) on the redistribution structure (S1/S2), wherein the second semiconductor structure (TD13/E1, TD23/E2) includes a second semiconductor die (TD13, TD23) and a second encapsulant (E1, E2) that encapsulates the second semiconductor die (TD13, TD23, see Figure 2); and
a third semiconductor structure (TD11 and E1 in the first structure, TD21 and E2 in the second structure) on the redistribution structure (S1, S2), wherein the third semiconductor structure (TD11/E1, TD21/E2) includes a third semiconductor die (TD11, TD21) and a third encapsulant (E1, E2) that encapsulates the third semiconductor die (TD11, TD21), wherein the third semiconductor structure (TD11/E1, TD21/E2) is electrically insulated from the substrate (CL/BL2), the first semiconductor structure (TD12/E1, TD22/E2) and the second semiconductor structure (TD13/E1, TD23/E2, due to the dies/structures TD11, TD12, TD13, TD21, TD22, TD23, having means of electrical insulation surrounding the electrical connections therefor, see the lower surfaces of each die having electrical interconnects in Figure 2, the third semiconductor structure would be electrically insulated from the other dies through the electrical insulation material, further, the substrate comprises insulating material 106B, thus the third semiconductor die TD11/E1, TD21/E2 is electrically insulated from the substrate insulating material 106B, otherwise, one having ordinary skill in the art would recognize that there would be electrical shorts in the device due to the wiring of the components, substrates, RDLs, interposers, etc., being electrically insulated with insulating material),
wherein the third semiconductor structures (TD11/E1, TD21/E2) of the first structure (P1) and the second structure (P2) are disposed adjacent to two corners or two edges of the substrate (CL/BL2) in a top plan view of the substrate (see Figure 3, which shows each third semiconductor structure of each structure P1/P2 are either disposed adjacent to a corner or edge of the substrate, where the synonyms to “adjacent” are “nearby” or “next to”).
Note that the Examiner has construed the claimed first, second, and third encapsulants as the encapsulation layers E1/E2 of Lu because all the claimed first, second, and third encapsulants are formed of the same material, a molding compound, see para. [0034] of the instant specification, and the encapsulation layers E1/E2 of Lu is also made of a molding compound, see para. [0032] of Lu. Moreover, the structure of the encapsulants as claimed is the same as the structure of the encapsulation layers E1/E2 of Lu.
Regarding claim 16, Lu discloses wherein no electrical signal is transmitted from the third semiconductor structures (TD11/E1, TD21/E2) of the first structure (P1) and the second structure (P2) to any of the first semiconductor structures (TD12/E1, TD22/E2) and the second semiconductor structures (TD13/E1, TD23/E2) of the first structure (P1) and the second structure (P2, see again para. [0030] and [0037], the third dies of the third semiconductor structures are a non-operating die, a die configured for non-use, or a die without devices therein, therefore no electrical signals would be transmitted therethrough to other components of the device).
Regarding claim 17, Lu discloses wherein the third semiconductor structure (TD11/E1, TD21/E2) of each of the first structure (P1) and the second structure (P2) is disposed adjacent to a corner or an edge of the interposer (S1/S2) in the top plan view of the interposer (S1/S2, see Figure 3).
Regarding claim 19, Lu discloses wherein in each of the first structure (P1) and the second structure (P2), the second semiconductor structure (TD13/E1, TD23/E2) and the third semiconductor structure (TD11/E1, TD21/E2) are disposed at opposite sides of the first semiconductor structure (TD12/E1, TD22/E2, see Figure 2C).
Regarding claim 20, Lu discloses wherein in each of the first structure (P1) and the second structure (P2), an arrangement of the second semiconductor die (TD13, TD23) and the second encapsulant (E1, E2) is identical to an arrangement of the third semiconductor die (TD11, TD21) and the third encapsulant (E1, E2, 620, the encapsulant E1, E2 is considered to be the first, second, and third encapsulants because the monolithic structure of the encapsulant E1, E2 encapsulates all three semiconductor dies, see Figure 2 which shows the structure of the encapsulant over each die in each structure P1, P2, is identical, i.e. covers upper and lateral surfaces of the semiconductor dies).
Regarding claim 21, Lu discloses wherein in each of the first structure (P1) and the second structure P2), the third encapsulant (E1, E2) comprises the same material as the second encapsulant (E1, E2, since the encapsulant of each semiconductor structure is the same encapsulant, they are made of the same material).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Nam as applied to claim 5 above, and further in view of Lin et al. (“Lin” US 2018/0151502).
Regarding claim 6, Nam does not disclose wherein the third semiconductor die of the third semiconductor structure is grounded.
Lin discloses, however, connecting a dummy die (106) to a ground node through metal pillars (40), see para. [0052] of Lin.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin above into the teachings of Nam to include the ground connection of the third semiconductor die, the dummy die of Nam. The claimed elements were known in the prior art before the effective filing date of the present invention, and the combination of the prior art would result in the predictable result of providing ground connection for the device to improve electromagnetic shielding. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Nam as applied to claim 1 above, and further in view of Cheng et al. (“Cheng” US 2021/0183844).
Regarding claim 8, Nam further discloses conductive components (450) disposed between the redistribution structure (360) and the first semiconductor structure (400M-1/620), the second semiconductor structure (400CP/620) and the third semiconductor structure (400D/620, see Figure 2C);
an underfill layer (480) surrounding the conductive components (450) and filling gaps between the conductive components (450, see Figure 2C), wherein the underfill layer (480) is adjacent to the third encapsulant (620, see Figure 2C).
Nam does not disclose a molding compound as claimed.
Cheng discloses in Figure 2J, however, a molding compound (UF1, comprised of common mold materials, see para. [0027]) surrounding the first semiconductor structure (110), the second semiconductor structure (120), the third semiconductor structure (130) and the underfill layer (polymer layer 118 underneath the first semiconductor structure 110).
It would have been obvious to one having ordinary skill in the art to incorporate the molding compound as taught by Cheng into the teachings of Nam to further protect the components of the devices in the package.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lu as applied to claim 15 above, and further in view of Lin et al. (“Lin” US 2018/0151502).
Regarding claim 18, Lu discloses wherein in each of the first structure (P1) and the second structure (P2), the first semiconductor structure (TD12/E1, TD22/E2) and the second semiconductor structure (TD13/E1, TD23/E2) are electrically connected to the substrate (CL/BL2) by the redistribution structure (S1, S2) and conductive pillars of the interposer (vias 108A of interposer BL1).
Lu does not disclose while the third semiconductor die of the third semiconductor structure is grounded.
Lin discloses, however, connecting a dummy die (106) to a ground node through metal pillars (40), see para. [0052] of Lin.
It would have been obvious to one having ordinary skill in the art to incorporate the teachings of Lin above into the teachings of Lu to include the ground connection of the third semiconductor die of the third semiconductor structure, the dummy die of Lu. The claimed elements were known in the prior art before the effective filing date of the present invention, and the combination of the prior art would result in the predictable result of providing ground connection for the device to improve electromagnetic shielding. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Genevieve G Bullard-Connor whose telephone number is (571)270-0609. The examiner can normally be reached Mon-Fri, 9am-5pm.
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/Genevieve G Bullard-Connor/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899