DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/15/2026 has been entered.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 7-8, 10, and 12-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nomura (US Pub. No. 2018/0182706).
Regarding claim 1, in FIGs. 1-4 and 6, Nomura discloses an electrically programmable fuse, comprising: a first contact (PD1, see abstract); a second contact (PD2, see abstract) spaced from the first contact; a link (EF1, see abstract) between and electrically connecting the first contact and the second contact, wherein the first contact, the second contact and the link include semiconductor material (PS1, paragraph [0105]); a gate structure (IL1; broadly interpreted as a layer capable of being used in a non-functional gate structure) partially over the link, wherein an uncovered link region is uncovered by the gate structure; and a silicide region (MS1, paragraph [0105]) within the uncovered link region, wherein the link, the first contact and the second contact define a longitudinal axis, and the silicide region has a silicide width defined perpendicular to the longitudinal axis between a first edge of the silicide region that is parallel to the longitudinal axis and a second edge of the silicide region that is parallel to the longitudinal axis, and wherein the silicide region includes a first silicide region (e.g. within L1 in FIG. 1) within a first edge surface at the first edge of the link and a second silicide region (e.g. within L2 in FIG. 1) within a second edge surface at the second edge of the link, and wherein the gate structure is over a portion of the link and, in a direction of the silicide width, between the first silicide region and the second silicide region, and wherein each of the first and second silicide regions has a respective width (L1/L2) that is a portion of the silicide width.
Regarding claim 4, in FIGs. 1-4 and 6, Nomura discloses that at least one of the first contact and the second contact have a width defined perpendicular to the longitudinal axis larger than a link width defined perpendicular to the longitudinal axis between a first edge of the link and a second edge of the link.
Regarding claim 7, in FIGs. 1-4 and 6, Nomura discloses that the gate structure is over a center portion of the link.
Regarding claim 8, in FIGs. 1-4 and 6, Nomura discloses that the link has a link length between the first contact and the second contact and the first and second silicide regions are over an entirety of the link length.
Regarding claim 10, in FIGs. 1-4 and 6, Nomura discloses that the link has a link length between the first contact and the second contact and the gate structure is over only a portion of the link length.
Regarding claim 12, in FIGs. 1-4, 6, 14, and 16, Nomura discloses an electrically programmable fuse, comprising: a semiconductor fuse element (PS1, paragraph [0105]) including a first contact (PD1), a second contact (PD2) spaced from the first contact and a link between and electrically connecting the first contact and the second contact; a gate structure (IL1; broadly interpreted as a layer capable of being used in a non-functional gate structure) partially over the link, wherein an uncovered link region is uncovered by the gate structure, the link has a link length between the first contact and the second contact, and the gate structure is also over a portion of the link length and a portion of at least one of the first contact and the second contact (e.g. see FIGs. 14 and 16); and a silicide region (MS1, paragraph [0105]) within the uncovered link region.
Regarding claim 13, in FIGs. 1-4, 6, 14, and 16, Nomura discloses that the link, the first contact and the second contact define a longitudinal axis, and the silicide region has a silicide width defined perpendicular to the longitudinal axis between a first edge of the link and a second edge of the link.
Regarding claim 14, in FIGs. 1-4, 6, 14, and 16, Nomura discloses that the silicide region is between the first edge of the link and the second edge of the link.
Regarding claim 15, in FIGs. 1-4, 6, 14, and 16, Nomura discloses that the silicide region is within only one of a first edge surface at the first edge of the link and a second edge surface at the second edge of the link and the gate structure is over a remaining portion of the link.
Regarding claim 16, in FIGs. 1-4, 6, 14, and 16, Nomura discloses that the link has a link length between the first contact and the second contact and the silicide region extends an entirety of the link length (e.g. see FIG. 6).
Regarding claim 17, in FIGs. 1-4, 6, 14, and 16, Nomura discloses that the gate structure is over an entirety of the link length (e.g. see FIG. 16).
Regarding claim 18, in FIGs. 1-4, 6, 14, and 16, Nomura discloses a method, comprising: forming a semiconductor fuse element in a semiconductor layer (PS1, paragraph [0105]), the semiconductor fuse element including a first contact (PD1), a second contact (PD2) spaced from the first contact and a link between and electrically connecting the first contact and the second contact; forming a gate structure (IL1; broadly interpreted as a layer capable of being used in a non-functional gate structure) partially over the link and over a portion of at least one of the first contact and the second contact (e.g. see. FIG. 16), wherein an uncovered link region is uncovered by the gate structure; and forming a silicide region (MS1, paragraph [0105]) within the uncovered link region.
Allowable Subject Matter
Claims 2 and 19-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-2, 4-6, 8, and 10 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUCKER J WRIGHT whose telephone number is (571)270-3234. The examiner can normally be reached 8:30am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TUCKER J WRIGHT/ Primary Examiner, Art Unit 2891