DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because:
Number “0107-0280” appears in every page of the drawings.
Fig. 5C, correct reference number “276”, the terminal to --278--, the capping.
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation “a third conductive bus structure that connects the first row of contact structures with the first edge of the resistive layer” and “a third conductive bus structure that connects the second row of contact structures with the second edge of the resistive layer” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: in paragraph 0050, after “rows of vias” replace 266 with --268--, the vias for bus structure 272.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-12 and 14-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karino, US Pub. 2020/0395151.
Regarding claim 1, Karino teaches a semiconductor resistor structure (polysilicon resistor structure; see at least paragraph 0044), comprising:
a resistive layer (polysilicon resistor 31; see at least paragraph 0044 and figs. 1 and 2, the first example), a row of contact structures located at or near an edge of the resistive layer (row of contacts structure 62a; see at least fig. 1); and
a conductive bus structure (reference number 52a) comprising:
a first edge region (bottom edge region) connected to the row of contact structures;
a second edge region (another region not in direct contact with the contact structure) that is opposite the first edge region; and
an electrical terminal (terminal is the flat portion above the row contact 63a; see paragraph 0054 and fig. 2),
wherein, in a top-down view of the semiconductor resistor structure, a location of the electrical terminal (center of the terminal) is at or near an approximate mid-axis of the row of contact structures (62a) and at or near the second edge region (region that connected to the row contact structure 63a).
Regarding claim 2, see fig. 1 of Karino (resistive layer 31a is rectangular shaped).
Regarding claim 3, Karino teaches the semiconductor resistor structure of claim 1, wherein the electrical terminal (terminal is above the row contacts 63a) is a protrusion that extends away from the second edge region of the conductive bus structure and away from a center of the resistive layer (away from center of the resistive layer 31a).
Regarding claim 6, Karino teaches the semiconductor resistor structure of claim 1, wherein a width of the conductive bus structure is greater relative to a length of the conductive bus structure (width being the y-axis and length being the x-axis of the rectangular structure by reference number 52a; see fig. 1).
Regarding claim 7, Karino teaches the length of the conductive bus structure having a range of approximately 0.3 microns to approximately 1.5 microns (the length of the conductive bus structure 52a, which may be a stacked film, the length ranges between 120 nm to about 3 microns in the y-axis direction (see paragraph 0057 and fig. 2).
Regarding claim 8, Karino teaches the semiconductor resistor structure of claim 1, wherein the conductive bus structure comprises: a tungsten material, a copper material, a titanium material, a titanium nitride material, a tantalum material, or a tantalum nitride material (at least a copper, titanium and/or titanium nitride; see paragraph 0057).
Regarding claim 9, Karino teaches the semiconductor resistor structure (see above discussion for claim 1), comprising:
a resistive layer (31a);
a first conductive bus structure above (slope structure by reference number 52a; see fig. 2) and along a first edge of the resistive layer,
wherein, in a top-down view of the semiconductor resistor structure, the first conductive bus structure has a first length;
a first row of contact structures (62a) between the first conductive bus structure and along the first edge of the resistive layer (31a),
wherein the first row of contact structures (62a) electrically connects the first conductive bus structure 52a) to the first edge of the resistive layer (31a);
a second conductive bus structure (51) above and along a second edge of the resistive layer (31a),
wherein the second edge is opposite the first edge (see fig. 2), and
wherein, in the top-down view of the semiconductor resistor structure, the second conductive bus structure has a second length; and
a second row of contact structures (61a) between the second conductive bus structure (51) and along the second edge of the resistive layer (31a),
wherein the second row of contact structures (61a) electrically connects the second conductive bus structure (51) to the second edge of the resistive layer (31a), and
wherein, in the top-down view of the semiconductor resistor structure, a distance between the second row of contact structures and the first row of contact structures is lesser relative to the first length of the first conductive bus structure or the second length of the second conductive bus structure (see fig. 1).
Regarding claim 10, Karino teaches a third conductive bus structure (flat/narrow portion of the contact 62 that directly contacts the resistive layer; see fig. 2) connecting the first row of contact structures (wider portion of 62a) with the first edge of the resistive layer (31a).
Regarding claim 11, Karino teaches a third conductive bus structure (flat/narrow portion of the contact 61a that directly contacts the resistive layer 31a; see fig. 2) connecting the second row of contact structures (wider portion of 61a) with the second edge of the resistive layer (31a).
Regarding claim 12, Karino teaches using TaN (paragraph 0046), the TaN having an impedance between 25 to 200 Ohms/sq. Karino further teaches structural changes to his semiconductor resistor reduces the impedance during operation at high frequency operation (paragraph 0107).
Regarding claim 14, Karino teaches the method, comprising:
forming a row of contact structures (62a; see figs. 1 and 2) along a length-wise edge of an approximately rectangular-shaped resistive layer (31a);
forming a dielectric layer over the row of contact structures (Si3N4 layer 7);
forming a recess (recess for via connection) in the dielectric layer having a first side that is biased near the row of contact structures (62a) and a second side that is opposite the first side and biased away from the row of contact structures (the recess biased away from the contact structure 62a),
wherein the recess exposes the row of contact structures (62a); and
forming a conductive bus structure (52a) in the recess, wherein
forming the conductive bus structure electrically connects the conductive bus structure to the approximately rectangular-shaped resistive layer through the row of contact structures (see fig. 2).
Regarding claim 15, Karino teaches the method of claim 14, wherein forming the recess includes:
forming an approximately rectangular-shaped recess, wherein the first side is a length-wise side of the approximately rectangular-shaped recess (both resistive layer and the conductive bus structure are rectangular in shape; see at least fig. 1).
Regarding claim 16, Karino teaches the method of claim 15, wherein forming the recess includes forming a cavity that extends laterally (towards row contact 63) from an approximate midpoint of the second side and away from the first side (closer to the resistive layer), and wherein forming the conductive bus structure includes:
forming an electrical terminal (terminal is above the row contacts 63a; see fig. 2) in the cavity.
Regarding claim 17, Karino teaches the method of claim 14, wherein forming the conductive bus structure includes forming a first conductive bus structure (52a) for a first thin film resistor structure (thin film resistive layer 31a and 31c; see paragraph 0041 and fig. 2), and further comprising:
forming a second conductive bus structure (52c) for a second thin film resistor structure (31c), and forming a connection structure between the second conductive bus structure and the first conductive bus structure to connect, in electrical parallel (see fig. 24 and paragraph 0103), the second thin film resistor structure with the first thin film resistor structure.
Regarding claim 18, Karino teaches the method of claim 17, wherein forming the first conductive bus structure (52a) and forming the second conductive bus structure (52c) collectively comprises:
performing a deposition operation that concurrently forms the first conductive bus structure and the second conductive bus structure (see figs. 10 and 11).
Regarding claim 19, Karino teaches the method of claim 18, wherein the deposition operation is a first deposition operation and forming the connection structure (connection structure 5; see fig. 10) comprises:
performing a second deposition operation as part of forming the connection structure (connection structure 51 for the first and second resistive layers 31a and 31c, respectively).
Regarding claim 20, Karino teaches the method of claim 17, wherein forming the first conductive bus structure, forming the second conductive bus structure, and forming the connection structure collectively includes:
performing a deposition operation (see figs. 10 and 11) that concurrently forms the first conductive bus structure (52a), the second conductive bus structure (52c), and the connection structure (51).
Regarding claims 1 and 5, Karino teaches a semiconductor resistor structure (polysilicon resistor structure; see at least paragraphs 0044 and 0098-0101, the sixth example), comprising:
a resistive layer (polysilicon resistor 31b; see at least paragraph 0044 and figs. 21-22), a row of contact structures located at or near an edge of the resistive layer (row of contacts structure 61b; see at least figs. 21-22); and
a conductive bus structure comprising:
a first edge region (bottom edge region) connected to the row of contact structures;
a second edge region (another region not in direct contact with the row contact structure) that is opposite the first edge region; and
an electrical terminal (terminal 51a is connected to the row contact 61b in figs. 21-22),
wherein, in a top-down view of the semiconductor resistor structure, a location of the electrical terminal (center of the terminal) is at or near an approximate mid-axis of the row of contact structures (61b) and at or near the second edge region (region not in direct contact with the row contact structure 61b), and
wherein the electrical terminal is an area of the second edge region that connects with a vertical interconnect access structure above the second edge region (via connection 7a for connecting the terminal 51a; see fig. 22 and paragraphs 0083, 0098).
Claims 1 and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karino et al., US Pub. 2019/0181089 (Karino’089).
Regarding claim 1, Karino’089 teaches (see figs. 1 and 3) a semiconductor resistor structure (polysilicon resistor structure; see at least paragraphs 0034-0035), comprising:
a resistive layer (polysilicon resistor 3a),
a row of contact structures (see figs. 6-7) located at or near an edge of the resistive layer (row of contact structures, reference numbers 6a and 61a, in fig. 1 and fig. 6, respectively; see at least figs. 1, 3 and 6-7); and
a conductive bus structure comprising:
a first edge region (bottom edge region) connected to the row of contact structures (6a or 61a);
a second edge region (another region not in direct contact with the row contact structure) that is opposite the first edge region; and
an electrical terminal (terminal 5a is connected to the row contact 6a in figs. 1, 3 and 6),
wherein, in a top-down view of the semiconductor resistor structure, a location of the electrical terminal (center of the terminal) is at or near an approximate mid-axis of the row of contact structures (61; see fig. 6) and at or near the second edge region (region not in direct contact with the row contact structure 61), and
wherein the electrical terminal is an area of the second edge region that connects with a vertical interconnect access structure above the second edge region (via connection 7a for connecting the terminal 5a; see fig. 1 and paragraph 0041).
Regarding claim 4, Karino’089 teaches the terminal having a width of protrusion (the terminal) being greater than approximately 0.3 microns (0.9 mm; see paragraph 0042) and a length of the protrusion being greater than approximately 0.14 microns (2.0 mm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Karino (Karino ‘151).
Regarding claim 13, Karino teaches the claimed invention, except Karino does not specify a variation of resistance of being less than approximately 15%.
Karino, however, teaches that the resistance values are regulated by controlling the doping of the resistive material (controlled TCR to reduce changes in resistance to about zero) and adjusting the width and the length of the resistive layer (see paragraphs 0044-0046).
It would have been obvious to one skilled in the art before the effective filing date of the claimed invention to have met the variation of resistance claimed, since Karino teaches that the resistance variations are controllable by adjusting the size, shape of the resistive layer and/or by controlling the doping level to the resistive material, so as to adjust the variation of resistance being less than approximately 15%.
Conclusion
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/KYUNG S LEE/Primary Examiner, Art Unit 2833