DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed November 3, 2025 fails to comply with 37 CFR 1.98(a)(2), which requires a legible copy of each cited foreign patent document; each non-patent literature publication or that portion which caused it to be listed; and all other information or that portion which caused it to be listed. It has been placed in the application file, but the information referred to therein has not been considered.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-13 and 19, is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2021/0296237) in view of Chang et al. (2018/0190586).
Kim et al. show in Figs. 1A-1C and related text:
As for claim 1, a semiconductor device, comprising:
an active region ACT;
an isolation region 302 disposed on a side surface of the active region;
a gate trench intersecting the active region and extending into the isolation region;
a gate structure 307/WL/310 disposed in the gate trench;
a first impurity region 312a and a second impurity region 312b disposed in the active region on both sides of the gate structure and spaced apart from each other;
a bit line structure DC/(upper portion of) 330/332/BLC including a line portion (upper portion of) 330/332/BLC intersecting the gate structure and a plug portion DC disposed below the line portion and electrically connected to the first impurity region; and
an insulating structure 22/321/341 disposed on a side surface of the plug portion, wherein the insulating structure includes:
a spacer 22 including a first material (silicon oxide: [0082]);
an insulating pattern 341 disposed between the plug portion and the spacer and including a second material different from the first material (silicon oxynitride: [0052]); and
an insulating liner 321 covering a side surface and a bottom surface of the insulating pattern and including a third material different from the first material and the second material (silicon nitride: [0059]).
As for claim 19, a semiconductor device, comprising:
an insulating structure 22/321/341 having a first side and a second side opposing each other;
a first conductive region DC disposed on the first side of the insulating structure; and
a second conductive region BC disposed on the second side of the insulating structure,
wherein the insulating structure includes:
a spacer being 22 in contact with the second conductive region and including a first material (silicon oxide: [0082]);
an insulating pattern 341 disposed between the first conductive region and the spacer and including a second material different from the first material (silicon oxynitride: [0052]); and
an insulating liner 321 covering a side surface and a bottom surface of the insulating pattern and including a third material different from the first material and the second material (silicon nitride: [0059]).
Kim et al. do not disclose a level of a bottom surface of the insulating liner is lower than a level of a bottom surface of the spacer.
Chang et al. teach in Fig. 8 and related text a level of a bottom surface of the insulating liner 50 is lower than a level of a bottom surface of the spacer 30.
Kim et al. and Chang et al. are analogous art because they are directed to a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified feature(s) of Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to a level of a bottom surface of the insulating liner being lower than a level of a bottom surface of the spacer, as taught by Chang et al., in Kim et al.’s device, in order to improve the electric isolation of the device.
As for claim 3, the combined device shows the spacer includes a first material layer (lower portion of) 22 including the first material, and a second material layer (interfacial region between upper portion of 22 and lower portion of 321) including the second material, and
wherein the second material layer is disposed between the first material layer and the insulating liner (Kim: silicon oxynitride: [0082]).
As for claim 4, Kim et al. and Chang et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except a distance between both side surfaces of the spacer is in a range from about 3 Å to about 10 Å.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a distance between both side surfaces of the spacer is in a range from about 3 Å to about 10 Å, in order to optimize the performance of the device. Furthermore, it has been held that where then general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Furthermore, it has been held in that the applicant must show that a particular range is critical, generally by showing that the claimed range achieves unexpected results relative to the prior art range. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990). Note that the law is replete with cases in which when the mere difference between the claimed invention and the prior art is some dimensional limitation or other variable within the claims, patentability cannot be found. The instant disclosure does not set forth evidence ascribing unexpected results due to the claimed dimensions. See Gardner v. TEC Systems, Inc., 725 F.2d 1338 (Fed. Cir. 1984), which held that the dimensional limitations failed to point out a feature which performed and operated any differently from the prior art.
As for claim 5, the combined device shows a distance between both side surfaces of the spacer is smaller than a width of the insulating pattern (Kim: Fig. 1B).
As for claim 6, the combined device shows an upper surface of the first impurity region is disposed at a level lower than a level of an upper surface of the second impurity region, and
wherein at least a portion of the insulating structure is disposed between the second impurity region and the plug portion (Kim: Fig. 1B).
As for claim 7, the combined device shows a pad pattern (lower portion of) BC disposed on and contacting the second impurity region; and
an insulating barrier pattern 10 being in contact with a portion of a side surface of the pad pattern,
wherein the pad pattern includes a first side surface in contact with the insulating barrier pattern and a second side surface in contact with the spacer (Kim: Fig. 1B).
As for claim 8, the combined device shows the pad pattern includes doped polysilicon (Kim: [0057]).
As for claim 9, the combined device shows a buffer structure 20P/(lower portion of) 330,
wherein at least a portion of the buffer structure is disposed between the insulating barrier pattern and the line portion,
wherein the buffer structure includes a first buffer layer (lower portion of) 20P and a second buffer layer (middle portion of) 20P disposed on the first buffer layer, and wherein a material of the first buffer layer is different from a material of the second buffer layer (Kim: [0048], [0044]).
As for claim 10, the combined device shows the buffer structure further includes a third buffer layer (upper portion of) 20P disposed on the second buffer layer, and wherein a material of the third buffer layer is different from the material of the second buffer layer (Kim: [0048], [0044]).
As for claim 11, the combined device shows the buffer structure further includes a fourth buffer layer (lower portion of) 330 disposed on the third buffer layer, and wherein the fourth buffer layer is in contact with a lower surface of the line portion (kim: Fig. 1B).
As for claim 12, the combined device shows the fourth buffer layer is a polysilicon layer (Kim: [0050], lines 9-10).
As for claim 13, the combined device shows a contact structure (upper portion of) BC disposed on the pad pattern,
wherein the contact structure is in contact with the insulating structure and the pad pattern, and
wherein the spacer of the insulating structure is in contact with the contact structure (Kim: Fig. 1C).
Claim(s) 2 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2021/0296237) and Chang et al. (2018/0190586) in view of Song et al. (2020/0388679).
As for claims 2 and 20, Kim et al. and Chang et al. disclosed substantially the entire claimed invention, as applied to claims 1 and 19, respectively, above, including a lower end of the insulating liner is disposed at a level lower than a level of a lower end of the spacer,
wherein a portion of the insulating liner disposed between the insulating pattern and the first conductive region is in contact with the first conductive region,
wherein a distance between both side surfaces of the spacer is smaller than a width of the insulating pattern,
wherein the second material is silicon nitride, and
wherein the third material is silicon oxide.
Kim et al. and Chang et al. do not disclose the first material is silicon carbonitride.
Song et al. teach in Fig. 11 and related text the first material 156 is silicon carbonitride (claims 2 and 20); and each of the first spacer and the second spacer 156 includes a silicon carbonitride material ([0123]-[0124]).
Kim et al., Chang et al. and Song et al. are analogous art because they are directed to a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. and Chang et al. with the specified feature(s) of Song et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use silicon carbonitride, as the first material, as taught by Song et al., in Kim et al. and Chang et al.'s device, in order to reduce or suppress the infiltration of impurities, minimize the interconnect parasitic capacitance and increase the device speed.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2021/0296237) in view of Song et al. (2020/0388679) and Chang et al. (2018/0190586).
As for claim 14, Kim et al. show in Figs. 1A-1C and related text a semiconductor device, comprising:
an active region ACT;
an isolation region 302 disposed on a side surface of the active region;
a gate trench intersecting the active region and extending into the isolation region;
a gate structure 307/WL/310 disposed in the gate trench;
a first impurity region 312a and a second impurity region 312b disposed in the active region on both sides of the gate structure and spaced apart from each other;
a bit line structure DC/(upper portion of) 330/332/BLC including a line portion (upper portion of) 330/332/BLC intersecting the gate structure and a plug portion DC disposed below the line portion and electrically connected to the first impurity region;
a first insulating structure 22/321/341 disposed on a first side surface of the plug portion; and
a second insulating structure 22 disposed on a second side surface of the plug portion and vertically overlapping the line portion,
wherein the first side surface of the plug portion is aligned with a side surface of the line portion,
wherein the second side surface of the plug portion vertically overlaps a lower surface of the line portion,
wherein at least a portion of the first insulating structure is disposed between the plug portion and the second impurity region,
wherein the first insulating structure includes a first spacer 22, an insulating pattern 341 disposed between the first spacer and the first side surface of the plug portion, and an insulating liner 321 covering a side surface and a bottom surface of the insulating pattern,
wherein the second insulating structure includes a second spacer (lower portion of) 22, and a third spacer disposed (upper portion of) 22 between the second spacer and the second side surface of the plug portion, and
wherein the insulating pattern includes a material different from the silicon carbonitride material (silicon oxynitride: [0052]).
Kim et al. do not disclose each of the first spacer and the second spacer includes a silicon carbonitride material; and a level of a bottom surface of the insulating liner is lower than a level of a bottom surface of the spacer.
Song et al. teach in Fig. 11 and related text the first material 156 is silicon carbonitride (claims 2 and 20); and each of the first spacer (left one of) 156 and the second spacer (right one of) 156 includes a silicon carbonitride material ([0123]-[0124]).
Chang et al. teach in Fig. 8 and related text a level of a bottom surface of the insulating liner 50 is lower than a level of a bottom surface of the spacer 30.
Kim et al., Song et al. and Chang et al. are analogous art because they are directed to a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al. with the specified feature(s) of Song et al. and Chang et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use silicon carbonitride, as the first material and as the first and second spacers, as taught by Song et al., and a level of a bottom surface of the insulating liner is lower than a level of a bottom surface of the spacer, as taught by Chang et al., in Kim et al.'s device, in order to reduce or suppress the infiltration of impurities, minimize the interconnect parasitic capacitance, increase the device speed and improve the electric isolation of the device.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (2021/0296237), Song et al. (2020/0388679) and Chang et al. (2018/0190586) in view of Jung et al. (20160163637).
As for claims 15, Kim et al., Song et al. and Chang et al. disclosed substantially the entire claimed invention, as applied to claim 14 above, including a pad pattern BC disposed on and contacting the second impurity region;
an insulating barrier pattern 10 being in contact with a portion of a side surface of the pad pattern; and
a buffer structure 20P disposed on the insulating barrier pattern,
wherein at least a portion of the insulating barrier pattern vertically overlaps the line portion,
wherein the buffer structure is in contact with an upper surface of the insulating barrier pattern and the lower surface of the line portion,
wherein the pad pattern includes a first side surface in contact with the insulating barrier pattern and a second side surface in contact with the first spacer,
wherein the insulating pattern includes silicon nitride (Kim: [0052]).
Kim et al., Song et al. and Chang et al. do not disclose the insulating liner includes silicon oxide.
Jung et al. teach in Figs. 1-4 and related text the insulating liner 144 (143) includes silicon oxide ([0104]).
Kim et al., Song et al., Chang et al. and Jung et al. are analogous art because they are directed to a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kim et al., Song et al. and Chang et al. with the specified feature(s) of Jung et al. because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use silicon oxide, as the insulating liner, as taught by Jung et al., in Kim et al., Song et al. and Chang et al.'s device, in order to prevent short circuits and crosstalk, reduce interface traps and leakage and improve device reliability.
Furthermore, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416 (CCPA 1960).
As for claims 16, the combined device shows the second spacer is in contact with the insulating barrier pattern and the buffer structure below the line portion (Kim: Fig. 1B).
As for claims 17, the combined device shows the buffer structure includes a first buffer layer (lower portion of) 20P and a second buffer layer (upper portion of) 20P disposed on the first buffer layer,
wherein the first buffer layer includes silicon oxide ([0044], [0048]),
wherein the second buffer layer includes silicon nitride ([0044], [0048]), and
wherein the second spacer is in contact with at least the first buffer layer and the second buffer layer of the buffer structure below the line portion (Kim: Fig. 1B).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-17, 19 and 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MEIYA LI/Primary Examiner, Art Unit 2811
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