DETAILED ACTION
This action is responsive to communications: RCE filed on 01/13/2026.
Applicant amended claims 1, 12, and 18; cancelled claims 3-4, 21; added new claims 22-23. Claims 1-2, 5-20, and 22-23 are pending. Claims 1, 12, and 18 are independent.
Continued Examination under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 01/13/2026 has been entered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority claimed.
5. Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7. Claims 1-2, 5-20, and 22-23 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention (See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968)). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention. For claims 1, 12, and 18, missing/ omitted elements, co-operative functions listed in bold in association with related vague limitations which are underlined.
Regarding independent claim 1, a device comprising: a PHY having an interface to support communication of command signals and data with a physical memory the PHY implementing:
a training mode to train the interface to communicate the command signals or data over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface; and (mechanism of weakening is not understood because description of necessary circuitry components is missing. Associated description from Specification para [0014], [0045], [0046], [0052], [0054], [0056], and [0061] needs to be incorporated)
an operational mode to use the interface to communicate the command signals or data over the operational voltage range using a parameter of the interface that is detected during the training mode. (Parameters, set of parameters need to be described since it is vague what kind of parameter is being referred. Associated description from Specification para [0014], [0045], [0046], [0052], [0054], [0056], and [0061] needs to be incorporated)
Regarding independent claim 12, a system comprising: a memory controller; a dynamic random-access memory (DRAM); and a PHY providing a communicative coupling with the memory controller and the DRAM and including an interface between the PHY and the DRAM, the PHY implementing: a training mode to detect a value of a parameter of the interface that defines how command signals and data are communicated over the interface as part of training the interface,
the training mode operational over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface; and
an operational mode to use the value for the parameter to implement the interface between the PHY and the DRAM, over the operational voltage range. (See claim 1 analysis)
Regarding independent claim 18, a method comprising: setting a training mode to train an interface between a PHY and a Physical memory to communicate command signals or data,
the training mode employing a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface; and
setting an operational mode to operate the interface between the PHY and the physical memory to communicate command signals or data,
the operational mode employing the operational voltage range by returning the terminations to operational strength and using at least one parameter of the interface that is detected during the training mode. (See claim 1 analysis)
All dependent claims inclusive of claims 1-2, 5-20, and 22-23 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
Claim Rejections - 35 USC § 102
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
10. Claims 1, 12, 18, and 22-23 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KIM et al. (US 2019/0080783 A1).
Regarding independent claim 1, KIM teaches a device (Fig. 1: 1000) comprising:
a PHY having an interface (para [0083]: “buffer memory device interface”, Fig. 5: 750) to support communication of command signals and data (para [0083]) with a physical memory (Fig. 1: 1300),
the PHY implementing:
a training mode (para [0089]: “ZQ calibration operation”) to train the interface to communicate the command signals or data over a training voltage range (Fig. 6 and para [0089]: combined “first reference voltage range” and “second reference voltage range”) that is widened relative to an operational voltage range (Fig. 6) by weakening terminations of the interface (Fig. 6, Fig. 11 in context of para [0131], para [0132]: “termination direction” and voltage division scheme of the calibration resistors employed to generate wide range of vref during training, calibration. See also para [0080], para [0084]); and
an operational mode (normal operation for one type of memory, e.g. LPDDR4) to use the interface to communicate the command signals or data over the operational voltage range using a parameter of the interface that is detected during the training mode (see para [0083]-para [0085], Fig. 6: vref associated with “second reference voltage range” is used for low power LPDDR4).
Regarding independent claim 12, KIM teaches a system (Fig. 1 system) comprising:
a memory controller (Fig. 1: 1200);
a dynamic random-access memory (DRAM) (Fig. 1: 1300, see para [0083]); and
a PHY (para [0083]: “buffer memory device interface”, Fig. 5: 750) providing a communicative coupling with the memory controller and the DRAM (para [0083]) and including an interface (See Fig. 2, Fig. 4) between the PHY and the DRAM,
the PHY (Fig. 5: 750) implementing:
a training mode (para [0089]: “ZQ calibration operation”) to detect a value of a parameter of the interface (reference voltage) that defines how command signals and data are communicated over the interface as part of training the interface (para [0083], para [0089]),
the training mode operational over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface (Fig. 6, Fig. 11 in context of para [0131], para [0132]: “termination direction” and voltage division scheme of the calibration resistors employed to generate wide range of vref during training, calibration. See also para [0080], para [0084]); and
an operational mode (normal operation for one type of memory, e.g. LPDDR4) to use the value for the parameter to implement the interface between the PHY and the DRAM, over the operational voltage range (see para [0083]-para [0085], Fig. 6: vref associated with “second reference voltage range” is used for low power LPDDR4).
Regarding independent claim 18, KIM teaches a method (method of operating Fig. 1 system, see Abstract, para [0008]) comprising:
setting a training mode to train an interface between a PHY and a Physical memory to communicate command signals or data (para [0083], para [0089]),
the training mode employing a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface (Fig. 6, Fig. 11 in context of para [0131], para [0132]: “termination direction” and voltage division scheme of the calibration resistors employed to generate wide range of vref during training, calibration. See also para [0080], para [0084]); and
setting an operational mode to operate the interface between the PHY and the physical memory to communicate command signals or data (Fig. 6, para [0083], para [0084]),
the operational mode employing the operational voltage range by returning the terminations to operational strength and using at least one parameter of the interface that is detected during the training mode (see para [0083]-para [0085], Fig. 6: vref associated with “second reference voltage range” is used for low power LPDDR4).
Regarding claim 22, KIM teaches the device of claim 1, wherein implementing the operational mode further includes returning the terminations to operational strength (in context of para [0008], para [0088], para [0097], Fig. 11: calibration resistors are not used during normal operation).
Regarding claim 23, LEE-461 and LEE-126 teach the device of claim 22, wherein returning the terminations to operational strength includes setting a value at a corresponding transistor to support higher data transfer speeds (in context of para [0008], para [0088], para [0097], Fig. 11: impedance is adjusted by using vref from the proper range).
.
Claim Rejections - 35 USC § 103
11. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
12. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
13. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claims 1-2, 5-6, 8, 10, 12, 15-16, 18, and 20 is/are rejected under 35 U.S.C. 103 as being obvious over LEE-461 (US 2018/0315461 A1), in view of LEE-126 (US 2022/0199126 A1).
Regarding independent claim 1, LEE-461 teaches a device (Fig. 16: 11 memory system, para [0123]-para [0124]) comprising:
a physical layer (PHY) having an interface (Fig. 16: RIC1. See Fig. 1: 50 “reception interface circuit”, para [0006]) to support communication of command signals and data with a physical memory (see Fig. 16: 41 memory device, para [0124], para [0126]),
the PHY implementing: a training mode (para [0043]: “training mode”) to train the interface (e.g., reference voltage search and training) over a training voltage range (Fig. 5, Fig. 6: VIH-VIL range) to communicate the command signals or data (Fig. 2: S200, para [0043]: search performed to find optimum code corresponding to “…optimal voltage level of the reference voltage VREF…”); and
an operational mode (para [0043], para [0049]: “normal mode”) to use the trained interface (Fig. 2: S300, para [0043], para [0049]) to communicate the command signals or data over an operational voltage range (range comprising Fig. 5: higher VREF of CV4 to Fig. 6: lower VREF of CV2. See para [0060], para [0061] for search and code selection)
LEE-461 is silent with respect to method of deriving training vref and operational voltage range that is smaller than the training voltage range.
LEE-126 teaches a training mode (para [0009]: “training mode”) to train the interface to communicate the command signals or data over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface (Fig. 18, Fig. 20A, para [0177], para [0186]: wide vref range vref1-vref3 is achieved, see Fig. 20A, employing Fig. 18 resistor scheme); and
an operational mode to use the interface to communicate the command signals or data over the operational voltage range using a parameter of the interface that is detected during the training mode (Fig. 18, Fig. 20A, para [0177], para [0186], para [0009], Fig. 21).
LEE-461 and LEE-126 are in analogous field of art because they are in the same field of endeavor of memory system vref training methodology.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-126’s DRAM memory system and training circuitry into the apparatus of LEE-461 such that claimed limitation can be implemented in order to have system benefits e.g., optimal eye decoding leading to improved performance when different devices are connected over a communication channel.
Regarding claim 2, LEE-461 and LEE-126 teach the device of claim 1. LEE-461 teaches wherein the interface implements an interface protocol that employs the parameter used to control communication of the command signals and the data with the physical memory (para [0041], para [0043], Fig. 21).
Regarding claim 5, LEE-461 and LEE-126 teach the device of claim 2. LEE-461 teaches wherein the parameter involves voltage reference (Vref) training, command training, clock-to-strobe leveling, write-leveling training, or strobe-to-DQ training of the interface protocol (LEE-461 para [0009]: VREF signal).
Regarding claim 6, LEE-461 and LEE-126 teach the device of claim 2. LEE-126 teaches wherein the parameter involves how signals are propagated from one physical memory component of the physical memory to another physical memory component of the physical memory (para [0097], para [0037]).
Regarding claim 8, LEE-461 and L SARASWAT teach the device of claim 1. LEE-461 teaches wherein the training mode is further configured to modify termination states or output impedances of the physical memory to implement the training voltage range as part of the training mode (LEE-461 Fig. 9A and para [0079]: RTT are selectively employed and output impedance of SB is changed).
Regarding claim 10, LEE-461 and LEE-631 teach the device of claim 1.
LEE-461 teaches wherein the PHY includes another interface to transfer command signals and data with a memory controller (see LEE-461 Fig. 16: RIC2).
Regarding independent claim 12, LEE-461 teaches a system (Fig. 16: 11 “memory system”, para [0123]-para [0124]) comprising:
a memory controller (Fig. 16: 21 memory controller);
a dynamic random-access memory (DRAM) (see Fig. 16: 41 memory device, para [0124]); and
a physical layer (PHY) (Fig. 16: RIC1. See Fig. 1: 50 “reception interface circuit”, para [0006]) providing a communicative coupling (para [0124], para [0126]) with the memory controller (para [0040], Fig. 1: 20) and the DRAM (para [0040], Fig. 1: 40),
the PHY implementing: a training mode (para [0043]: “training mode”) to detect a value of a parameter of the interface (vref for DQ transmission) that defines how command signals and data are communicated over the interface (para [0043]: search performed to find optimum code corresponding to “…optimal voltage level of the reference voltage VREF…”) as part of training the interface (Fig. 2: S200, para [0043]),
the training mode operational over a training voltage range (Fig. 5, Fig. 6: VIH-VIL range); and
an operational mode (para [0043], para [0049]: “normal mode”) to use the detected value for the parameter (search result with optimum code corresponding to “…optimal voltage level of the reference voltage VREF…”) to implement the interface between the PHY and the DRAM (Fig. 2: S300, para [0043], para [0049]),
the operational mode operational over an operational voltage range (range comprising Fig. 5: higher VREF of CV4 to Fig. 6: lower VREF of CV2. See para [0060], para [0061] for search and code selection).
LEE-461 is silent with respect to using DRAM memory system and operational voltage range being smaller than the training voltage range.
LEE-126 teaches a training mode (para [0009]: “training mode”) to detect a value of a parameter of the interface that defines how command signals and data are communicated over the interface as part of training the interface (Fig. 18, Fig. 20A, para [0177], para [0186]: wide vref range vref1-vref3 is achieved, see Fig. 20A, employing Fig. 18 resistor scheme),
the training mode operational over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface (Fig. 18, Fig. 20A, para [0177], para [0186]: wide vref range vref1-vref3 is achieved, see Fig. 20A, employing Fig. 18 resistor scheme); and
an operational mode to use the value for the parameter to implement the interface between the PHY and the DRAM, over the operational voltage range (Fig. 18, Fig. 20A, para [0177], para [0186], para [0009], Fig. 21).
LEE-461 and LEE-126 are in analogous field of art because they are in the same field of endeavor of memory system vref training methodology.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-126’s DRAM memory system and training circuitry into the apparatus of LEE-461 such that claimed limitation can be implemented in order to have system benefits e.g., optimal eye decoding leading to improved performance when different devices are connected over a communication channel.
Regarding claim 15, LEE-461 and LEE-126 teach the system of claim 12.
LEE-461 teaches wherein the parameter includes signal or timing (LEE-461 para [0009]).
Regarding claim 16, LEE-461 and LEE-126 teach the system of claim 12.
LEE-461 teaches wherein the parameter includes voltage reference (Vref) training. (LEE-461 para [0009]).
Regarding independent claim 18, LEE-461 and LEE-126 teach a method comprising: setting a training mode to train an interface between a physical layer (PHY) and physical memory to communicate command signals or data, the training mode employing a training voltage range; and setting an operational mode to operate the trained interface between the PHY and the physical memory to communicate command signals or data, the operational mode employing an operational voltage range that is less than the training voltage range, wherein the operational mode uses at least one parameter of the interface that is detected during the training mode.
(See claim 12 and claim 1 rejection analysis)
Regarding claim 20, LEE-461 and LEE-126 teach the method of claim 18, wherein the training of the interface is voltage reference (Vref) training. (See claim 12, claim 16 rejection analysis)
15. Claims 7, 9, 11, 13-14, 17, and 19 is/are rejected under 35 U.S.C. 103 as being obvious over LEE-461 (US 2018/0315461 A1), and LEE-126 (US 2022/0199126 A1), in further view of LEE-631 (US 2022/0148631 A1).
Regarding claim 7, LEE-461 and LEE-126 teach the device of claim 1. They are silent with respect to “…training mode is configured to modify termination states or output impedances of the PHY to implement the training voltage range of the training mode”.
LEE-631 teaches wherein the training mode is configured to modify termination states (see e.g., LEE-631 para [0048]-para [0050]. See also para [0038]-para [0039]) or output impedances of the PHY to implement the training voltage range of the training mode (see e.g., LEE-631 para [0048]-para [0049]).
LEE-631 teaches a system (Fig. 1: 10 “memory system”, para [0026]-para [0027]) comprising: a memory controller (Fig. 1: 100 memory controller); a dynamic random-access memory (DRAM) (Fig. 1: 120 memory device, para [0034]: DRAM) and associated physical layer (para [0034], para [0030]). LEE-631 Fig. 1 and para [0034] further teaches that disclosed “memory system” is architecturally compatible across several memory types e.g., DRAM, flash memory. LEE teaches reference voltage training operation and normal operation using vref. Para [0066], para [0073], Fig. 3 disclosure of LEE teaches setting optimal reference voltage via training and using trained vref in operation.
LEE-461, LEE-126 and LEE-631 are in analogous field of art because they are in the same field of endeavor of memory system vref training methodology.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461 and LEE-126 such that claimed limitation can be implemented in order to have system benefits e.g., control of per pin operation parameter and thus “…facilitating improvement of signal integrity…characteristics of data…” (LEE-631 para [0006], para [0123])
Regarding claim 9, LEE-461 and LEE-126 teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
LEE-631 teaches wherein the training mode operates at a frequency that is lower than a frequency of the operational mode (LEE-631 para [0027]-para [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461 and LEE-126 such that claimed limitation can be implemented in order to improve system performance.
Regarding claim 11, LEE-461 and LEE-126 teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
LEE-631 teaches wherein the PHY is implemented in hardware as part of an integrated circuit (LEE-631 Fig. 1: 106), the interface is bidirectional (LEE-631 Fig. 1 and para [0032]), and the physical memory is a dynamic random-access memory (DRAM) (LEE-631 para [0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461 and LEE-126 such that claimed limitation can be implemented in order to improve system performance.
Regarding claim 13, LEE-461 and LEE-631 teach the system of claim 12. They are silent with respect to remaining provisions of this claims.
LEE-631 teaches wherein the training mode is configured to modify termination states (see e.g., LEE-631 para [0048]-para [0050]. See also para [0038]-para [0039]) and output impedances of the PHY to implement the training voltage range of the training mode (see e.g., LEE-631 para [0048]-para [0049]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461 and LEE-126 such that claimed limitation can be implemented in order to improve system performance.
Regarding claim 14, LEE-461, LEE-126 and LEE-631 teach the system of claim 13. LEE-461 teaches wherein the training mode is further configured to modify termination states and output impedances of the dynamic random-access memory (DRAM) to implement the training voltage range as part of the training mode (LEE-461 Fig. 9A and para [0079]: RTT are selectively employed and output impedance of SB is changed).
Regarding claim 17, LEE-461 and LEE-126 teach the system of claim 12. They are silent with respect to remaining provisions of this claims.
LEE-631 teaches wherein the parameter includes command training, clock-to-strobe leveling, or strobe-to-DQ training (LEE-631: para [0036], para [0037]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461 and LEE-126 such that claimed limitation can be implemented in order to improve system performance.
Regarding claim 19, LEE-461, LEE-126 and LEE-631 teach the method of claim 18, wherein the training mode is configured to modify termination states and output impedances of the PHY to implement the training voltage range of the training mode. (See claim 13 rejection analysis)
Response to Arguments
Applicant’s arguments 01/13/2026 with respect to claim(s) 1, 12, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has not argued substantively against the dependent claim limitations and previous rejections are being relied upon.
Conclusion
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825