DETAILED ACTION
This action is responsive to communications: 04/28/2026.
Applicant amended claims 1, 2, 7, 8, 10, 12, 13, 14, 18, 19, 23, 23; cancelled claims 3-6, 15-17, 20-21; added new claims 24-29. Claims 1-2, 7-14,18-19, and 22-29 are pending. Claims 1, 12, and 18 are independent.
Information Disclosure Statement (IDS) filed on 02/16/2026 has been considered.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) MPEP 2163 guidelines teach that drawing and specification must be examined to assess whether an originally-filed claim has adequate support in the written disclosure and/or the drawings. Possession may be shown by a clear depiction of the invention in detailed drawings. C) Per MPEP 2173.04 “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Other passages and figures may apply as well. Per MPEP 2141.02 VI prior art must be considered in its entirety.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
No Priority
4. See ADS, no priority claimed.
5. Applicant is requested to check other claim informality, language issues (e.g., antecedent issues, redundant limitation issues, grammar issues) for all claims to expedite prosecution since informality scrutiny in this office action is not exhaustive and applicant’s co-operation is sought in this regard.
Claim Rejections - 35 USC § 112
6. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION. — The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
7a. Claims 1-2, 7-14,18-19, and 22-29 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential elements, such omission amounting to a gap between the elements. Such omission is tantamount to omitting essential structural cooperative relationships of elements also. See MPEP § 2172.01. A claim which omits subject matter disclosed to be essential to the invention as described in the specification or in other statements of record may be rejected as failing to claim the subject matter that the inventor or a joint inventor regards as the invention (See In re Mayhew, 527 F.2d 1229, 188 USPQ 356 (CCPA 1976); In re Venezia, 530 F.2d 956, 189 USPQ 149 (CCPA 1976); and In re Collier, 397 F.2d 1003, 158 USPQ 266 (CCPA 1968)). Such essential matter may include missing elements (circuitry components essential for function), steps or necessary structural cooperative relationships of elements described by the applicant(s) as necessary to practice the invention.
For claims 1, 12, and 18, missing/ omitted elements, co-operative functions listed in bold in association with related vague limitations which are highlighted.
1. A device comprising:
a PHY having an interface to support communication of command signals and data with a physical memory, the PHY implementing:
a training mode to train the interface to communicate the command signals or data over a training voltage range,
the training voltage range being made larger than an operational voltage range (“being made larger” limitation is unclear and it is not clear what circuitry is performing the function)
by weakening terminations of the interface, and (“weakening terminations “is not understood since claim does not clearly capture mechanism of weakening and description of necessary circuitry components is missing. Associated description from Specification para [0014], [0045], [0046], [0052], [0054], [0056], and [0061] provide multiple methods, schemes directed towards this limitation; but a specific method, scheme is not incorporated in claim language and the limitation is vague, indefinite. For example, mechanism such as modifying values of ODT resistors, or transistor circuitry/ switches or turning on/off specific circuitry is missing: for example, termination states and output impedances, for instance, are set using a value at a corresponding transistor. Setting the value at the corresponding transistor forces the signal to have a wider swing (e.g., rail-to-rail) in the training voltage range. Once training is completed (e.g., a portion of the training involving asynchronous feedback) the PHY returns to an operational voltage range using parameters detected during the training mode having a lesser amount of voltage swing to support higher data transfer speeds. Omission of such description makes the claimed limitation vague)
the training voltage range used to determine a voltage reference parameter; and
an operational mode to use the interface to communicate the command signals or data over the operational voltage range using the voltage reference parameter. (“voltage reference parameter” is not understood and need to be described since it is vague what kind of parameter is being referred. Associated description from Specification para [0014], [0045], [0046], [0052], [0054], [0056], and [0061) which provide multiple parameters, values directed towards this limitation; but a specific parameter is not incorporated in claim language. It is not clear which specific parameter is associated with this limitation and the limitation is vague, indefinite. For example, specific parameter such as DQ/ DQS timing, command timing is not described)
12. A system comprising:
a memory controller;
a dynamic random-access memory (DRAM); and
a PHY providing a communicative coupling with the memory controller and the DRAM and including an interface between the PHY and the DRAM, the PHY implementing:
a training mode to determine a value of a voltage reference parameter of the interface for communicating via the interface under operational conditions of the system,
the training mode operational over a training voltage range, and the training voltage range being made larger than an operational voltage range (“being made larger” limitation is unclear and it is not clear what circuitry is performing the function)
by weakening terminations of the interface; and (“weakening terminations “is not understood since claim does not clearly capture mechanism of weakening and description of necessary circuitry components is missing. Associated description from Specification para [0014], [0045], [0046], [0052], [0054], [0056], and [0061] provide multiple methods, schemes directed towards this limitation; but a specific method, scheme is not incorporated in claim language and the limitation is vague, indefinite. For example, mechanism such as modifying values of ODT resistors, or transistor circuitry/ switches or turning on/off specific circuitry is missing)
an operational mode to use the value for the voltage reference parameter as determined during the training mode to implement the interface for supporting communication between the PHY and the DRAM over the operational voltage range. (“voltage reference parameter” is not understood and need to be described since it is vague what kind of parameter is being referred. Associated description from Specification para [0014], [0045], [0046], [0052], [0054], [0056], and [0061) which provide multiple parameters, values directed towards this limitation; but a specific parameter is not incorporated in claim language. It is not clear which specific parameter is associated with this limitation and the limitation is vague, indefinite. For example, specific parameter such as DQ/ DQS timing, command timing is not described)
18. A method comprising:
implementing a training mode to train an interface between a PHY and a physical memory of a system to communicate command signals or data, over a training voltage range, the training voltage range being made larger than an operational voltage range by weakening terminations of the interface to determine a voltage reference parameter for supporting communication under operational conditions of the system; and
implementing an operational mode to operate the interface between the PHY and the physical memory to communicate the command signals or data over the operational voltage range,
the operational voltage range achieved using the voltage reference parameter as determined during the training mode and by returning the terminations to operational strength. (See claim 1 analysis)
All dependent claims inclusive of claims 1-2, 7-14,18-19, and 22-29 are rejected under this category. See art rejection for the interpretation of the art rejected claims.
7b. Claims 7, 14, 19, 23, and 28 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 7 (line 3), claim 14 (line 3), claim 19 (line 4), claim 23 (line 2-3), claim 28 (line 3) recite the term "values…corresponding transistors” which is unclear and vague. It is not clear what kind of value of the transistor is being referred in this context. It is not clear if value is referring to resistance value or threshold value or voltage value or any other kind of value. Limitation is vague, ambiguous. Correction is needed. No art rejection provided for these claims.
Claim Rejections - 35 USC § 103
8. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
9. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
10. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
11. Claims 1-2, 12, and 18 is/are rejected under 35 U.S.C. 103 as being obvious over LEE-461 (US 2018/0315461 A1), in view of LEE-126 (US 2022/0199126 A1) and Betts et al. (US 8,638,838 B1).
Regarding independent claim 1, LEE-461 teaches a device (Fig. 16: 11 memory system, para [0123]-para [0124) comprising:
a PHY having an interface (Fig. 16: RIC1. See Fig. 1: 50 “reception interface circuit”, para [0006]) to support communication of command signals and data with a physical memory (see Fig. 16: 41 memory device, para [0124], para [0126]),
the PHY implementing:
a training mode (para [0043]: “training mode”) to train the interface (e.g., reference voltage search and training) to communicate the command signals or data (Fig. 2: S200, para [0043]: search performed to find optimum code corresponding to “…optimal voltage level of the reference voltage VREF…”) over a training voltage range (Fig. 5, Fig. 6: VIH-VIL range),
the training voltage range being made larger than an operational voltage range by weakening terminations of the interface, and
the training voltage range used to determine a voltage reference parameter (para [0069]: control code); and
an operational mode (para [0043], para [0049]: “normal mode”) to use the interface (Fig. 2: S300, para [0043], para [0049]) to communicate the command signals or data over the operational voltage range using the voltage reference parameter (range comprising Fig. 5: higher VREF of CV4 to Fig. 6: lower VREF of CV2. See para [0060], para [0061] for search and code selection).
LEE-461 is silent with respect to method of deriving training vref and operational voltage range that is smaller than the training voltage range.
LEE-126 teaches a training mode (para [0009]: “training mode”) to train the interface to communicate the command signals or data over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface (Fig. 18, Fig. 20A, para [0177], para [0186]: wide vref range vref1-vref3 is achieved, see Fig. 20A, employing Fig. 18 resistor scheme); and an operational mode to use the interface to communicate the command signals or data over the operational voltage range using a parameter of the interface that is detected during the training mode (Fig. 18, Fig. 20A, para [0177], para [0186], para [0009], Fig. 21).
Betts teaches -
training or operation voltage range can be adjusted by adjusting terminations of the interface (col. 7, lines 405: “adjustable termination resistance circuit”. See Fig. 10 apparatus. See Fig. 14: 1412 in context of col. 19, lines 44-67, col. 20, lines 1-14: teaches voltage used for training or operation can be adjusted by adjusting termination)
LEE-461, LEE-126, and Betts are in analogous field of art because they are in the same field of endeavor of memory system vref training methodology.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-126’s training circuitry and Bett’s “adjustable termination resistance circuit” into the apparatus of LEE-461 such that claimed limitation can be implemented in order to have system benefits e.g., optimal eye decoding leading to improved performance when different devices are connected over a communication channel.
Regarding claim 2, LEE-461 and LEE-126 teach the device of claim 1.
LEE-461 teaches the interface implements an interface protocol under operational conditions of the device that employs the voltage reference parameter to control communication of the command signals and the data with the physical memory. (See para [0041], para [0043], Fig. 21).
Regarding independent claim 12, LEE-461 teaches a system (Fig. 16: 11 “memory system”, para [0123]-para [0124]) comprising:
a memory controller (Fig. 16: 21 memory controller);
a dynamic random-access memory (DRAM) (see Fig. 16: 41 memory device, para [0124]); and
a physical layer (PHY) (Fig. 16: RIC1. See Fig. 1: 50 “reception interface circuit”, para [0006]) providing a communicative coupling (para [0124], para [0126]) with the memory controller (para [0040], Fig. 1: 20) and the DRAM (para [0040], Fig. 1: 40),
the PHY implementing:
a training mode (para [0043]: “training mode”) to determine a value of a voltage reference parameter of the interface (vref for DQ timing) for communicating via the interface under operational conditions of the system (para [0043]: search performed to find optimum code corresponding to “…optimal voltage level of the reference voltage VREF…”),
the training mode operational over a training voltage range (Fig. 5, Fig. 6: VIH-VIL range), and
the training voltage range being made larger than an operational voltage range by weakening terminations of the interface; and
an operational mode (para [0043], para [0049]: “normal mode”) to use the value for the voltage reference parameter as determined during the training mode to implement the interface for supporting communication between the PHY and the DRAM over the operational voltage range (search result with optimum code corresponding to “…optimal voltage level of the reference voltage VREF…”. See Fig. 2: S300, para [0043], para [0049. See also range comprising Fig. 5: higher VREF of CV4 to Fig. 6: lower VREF of CV2. See para [0060], para [0061] for search and code selection).
LEE-461 is silent with respect to using DRAM memory system and operational voltage range being smaller than the training voltage range.
LEE-126 teaches a training mode (para [0009]: “training mode”) to detect a value of a parameter of the interface that defines how command signals and data are communicated over the interface as part of training the interface (Fig. 18, Fig. 20A, para [0177], para [0186]: wide vref range vref1-vref3 is achieved, see Fig. 20A, employing Fig. 18 resistor scheme),
the training mode operational over a training voltage range that is widened relative to an operational voltage range by weakening terminations of the interface (Fig. 18, Fig. 20A, para [0177], para [0186]: wide vref range vref1-vref3 is achieved, see Fig. 20A, employing Fig. 18 resistor scheme); and
an operational mode to use the value for the parameter to implement the interface between the PHY and the DRAM, over the operational voltage range (Fig. 18, Fig. 20A, para [0177], para [0186], para [0009], Fig. 21).
Betts teaches -
training or operation voltage range can be adjusted by adjusting terminations of the interface (col. 7, lines 405: “adjustable termination resistance circuit”. See Fig. 10 apparatus. See Fig. 14: 1412 in context of col. 19, lines 44-67, col. 20, lines 1-14: teaches voltage used for training or operation can be adjusted by adjusting termination)
LEE-461, LEE-126, and Betts are in analogous field of art because they are in the same field of endeavor of memory system vref training methodology.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-126’s training circuitry and Bett’s “adjustable termination resistance circuit” into the apparatus of LEE-461 such that claimed limitation can be implemented in order to have system benefits e.g., optimal eye decoding leading to improved performance when different devices are connected over a communication channel.
Regarding independent claim 18, LEE-461, LEE-126, and Betts teach a method comprising:
implementing a training mode to train an interface between a PHY and a physical memory of a system to communicate command signals or data, over a training voltage range, the training voltage range being made larger than an operational voltage range by weakening terminations of the interface to determine a voltage reference parameter for supporting communication under operational conditions of the system; and
implementing an operational mode to operate the interface between the PHY and the physical memory to communicate the command signals or data over the operational voltage range,
the operational voltage range achieved using the voltage reference parameter as determined during the training mode and by returning the terminations to operational strength. (this claim is drafted as in method format, substantially identical to the functionality recited in claim 12, and is therefore rejected for the same reasons as claim 12).
12. Claims 9, and 11 is/are rejected under 35 U.S.C. 103 as being obvious over LEE-461 (US 2018/0315461 A1), LEE-126 (US 2022/0199126 A1), Betts et al. (US 8,638,838 B1), in further view of LEE-631 (US 2022/0148631 A1).
Regarding claim 9, LEE-461, LEE-126, and Betts teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
LEE-631 teaches wherein the training mode operates at a frequency that is lower than a frequency of the operational mode (LEE-631 para [0027]-para [0028]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461, LEE-126, Betts such that claimed limitation can be implemented in order to improve system performance.
Regarding claim 11, LEE-461, LEE-126, and Betts teach the device of claim 1. They are silent with respect to remaining provisions of this claim.
LEE-631 teaches wherein the PHY is implemented in hardware as part of an integrated circuit (LEE-631 Fig. 1: 106), the interface is bidirectional (LEE-631 Fig. 1 and para [0032]), and the physical memory is a dynamic random-access memory (DRAM) (LEE-631 para [0034]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of LEE-631’s circuitry and method into the apparatus of LEE-461, LEE-126, Betts such that claimed limitation can be implemented in order to improve system performance.
Art rejection not provided for the remaining dependent claims. See 112b rejections.
Response to Arguments
Applicant’s arguments 04/28/2026 with respect to claim(s) 1, 12, and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Applicant has not argued substantively against the dependent claim limitations and previous rejections are being relied upon.
Applicant completely failed to respond to the 112b rejections set forth in the previous non-final office action and the rejections are being maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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