Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
In response to the Communications dated April 21, 2023, claims 1-8 are active in
this application.
Election
Michael Lenisa [Reg. No. 72,724] made a provisional election without traverse to prosecute the
invention of Group 1 directed to a DRAM read/write circuits, claims 1-8. Affirmation of this election was made in the response to the restriction requirements.
Specification
If there are cross-reference to related applications, please include the
respective patent numbers, if known.
Information Disclosure Statement
The information disclosure statements filed May 18, 2026 have been considered.
Claim Objections
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Rejections - 35 U.S.C. § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for
all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was
made.
Claims 1-3 and 5-8 are rejected under 35 U.S.C. § 103(a) as being unpatentable over Applicant’s
Admitted Prior Art [AAPA].
With respect to claim 1, AAPA discloses a circuit [figs. 3a and 3b] comprising: a read local bitline [RdLBL0]; and a plurality of pulldown transistor circuits [302’s] coupled to the read local bitline, a first one of the pulldown transistor circuits including: a first transistor [304], the first transistor including a first drain terminal coupled to the read local bitline; and a second low threshold voltage transistor [306], the second low threshold voltage transistor including a second drain terminal coupled to a first source terminal of the first transistor, the second low threshold voltage transistor to persist a voltage level detectable at a gate terminal of the second low threshold voltage transistor, the voltage level representative of a bit of information [“0”].
AAPA discloses all of the above mentioned but differs from the claimed invention only in that the AAPA utilizes high-threshold transistor coupled to the read local bitline, whereas the claimed recitation requires low-threshold transistor. It would have been obvious to a person of ordinary skill in the art at the time the invention was made to modify the circuit of fig. 3 by replacing the high-threshold transistor with low-threshold transistor. One of ordinary skill in the art would be motivated to make this substitution to improve the switching speed of the circuit and decrease propagation delay. It is well-known in the art that low-threshold transistors exhibit faster turn-on times compared to high-threshold transistors. The substitution represents a routine design choice among known alternative components to optimize circuit performance (balancing speed against leakage current) with entirely predictable results. As the circuit topology remains identical and the modification relies on the expected, inherent properties of low-threshold transistors, the claimed invention fails to patentably distinguish itself over the AAPA’s circuit under 35 USC 103.
With respect to claim 2, AAPA discloses, in fig. 3a, a keeper circuit [312] and a pre-charge circuit
[310] coupled to the read local bitline.
With respect to claim 3, AAPA discloses the plurality of pulldown transistor circuits include at least sixteen pulldown transistor circuits coupled to the read local bitline, the keeper circuit, and the pre-charge circuit. It is noted that the AAPA discloses seven times the pulldown transistor circuits, a skilled person in the art would have been motivated to duplicate or increase the number of parallel pull-down circuits to increase the total current-handling capability, accommodate wider input data buses (e.g., scaling logic functions). Thus, multiplying existing structural sub-circuits to increase operational capacity or performance bandwidth is a routine structural design. The combination of substituting thresholds and duplicating pull-down structures yields no unexpected results beyond what would be reasonably predicted by a standard combination of known elements.
With respect to claim 5, AAPA discloses the first and second low threshold voltage transistors are n-channel metal-oxide semiconductor (NMOS) transistors. See figs. 3a and 3b.
With respect to claim 6, AAPA discloses including: programmable circuitry; a network interface; and memory controller. See pars. 0055-0059. In the cited sections, AAPA indicates that the circuitry is part of a subsystem – therefore, it is inherent that the circuit : programmable circuitry; a network interface; and memory controller.
With respect to claim 7, AAPA discloses an integrated circuit chip that includes the circuit of claim 1, and further including: an interface; and at least one of a register file, a static random access memory, or a read-only-memory. See pars. 0055-0059. In the cited sections, AAPA indicates that the circuit is part of a subsystem that includes application of an SRAM.
With respect to claim 8, AAPA discloses a central processing unit that includes the circuit of claim 1, and further including: an interface; and at least one core. See pars. 0055-0059. In the cited sections, AAPA indicates that the Rdlbl circuits are inherently foundation, sub-level circuit structures belonging to the internal layout of ROM and SRAM memory arrays, any part or circuit contained inside those subsystems is sequentially contained within the broader CPU.
Allowable Subject Matter
The following is an Examiner's statement of reasons for the indication of
allowable subject matter: the prior art of records does not show (in addition to the other
elements in the claim) the following:
-with respect to claim 4: The circuit of claim 1, further comprising an ultra-low-temperature (ULT) and ultra-low-voltage (ULV) semiconductor material, the ultra-low-temperature (ULT) and ultra-low-voltage (ULV) semiconductor material to include the read local bitline and the plurality of pulldown transistor circuits.
Conclusion
For applicant’s benefit portions of the cited reference(s) have been cited to aid in
the review of the rejection(s). While every attempt has been made to be thorough and consistent within the rejection it is noted that the PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS. See MPEP 2141.02 VI.
When responding to the Office action, Applicants are advised to provide
the Examiner with line and page numbers of the application and/or references cited to assist the Examiner in the prosecution of this case.
Any inquiry concerning this communication or earlier communications
from the Examiner should be directed to Michael T. Tran whose telephone number is (571) 272-1795. Interview agendas may be emailed to Michael.tran@uspto.gov. The Examiner can normally be reached on Monday-Thursday from 6:00AM-4:30 P.M.
Any inquiry of a general nature or relating to the status of this application.
should be directed to the Group receptionist whose telephone number is (571) 272-1650.
/MICHAEL T TRAN/Primary Examiner, Art Unit 2827 September 9, 2026
Prosecution Insights