DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-8, 10-15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2018/0350961 A1 to Naito (hereinafter “Naito” – previously cited reference).
Regarding claim 1, Naito discloses a semiconductor device comprising: an active section having a transistor section and a diode section (semiconductor device 100 having active region with transistor section 70 and diode section 80; Fig. 2; paragraph [0078]); and an edge termination structure section provided to an outer circumference of the active section (edge termination structure surrounding active region; Fig. 1; paragraph [0079]), wherein the transistor section has a drift region of a first conductivity type which is provided in a semiconductor substrate (transistor section 70 has drift region 18 having n-type doping in substrate 10; Fig. 2; paragraph [0105]), a base region of a second conductivity type which is provided above the drift region (p-type base region 14 provided above drift region 18; Fig. 2; paragraph [0105]), a gate trench portion extending from a front surface of the semiconductor substrate to the drift region (trench portion extending from top surface of substrate 10 to drift region 18 as shown in Fig. 2), and a trench bottom portion of the second conductivity type which is provided in a lower end of the trench portion (trench bottom portion having p-type bottom region 17 disposed at lower end of trench portion; Figs. 2 and 32; paragraph [0206]), and the diode section is provided between a transistor section in proximity to the edge termination structure section, and the edge termination structure section in a top view (diode section 80 provided between transistor section 70 in the active region and the edge termination structure surrounding the active region; Figs 1 and 2; paragraph [0078]), and the trench bottom portion covers the bottom of the gate trench portion (bottom region 17 may cover at least a part of the bottom portion of gate trench portion 40; Figs. 1, 2 and 32; described specifically in paragraph [0210]).
Regarding claim 2, Naito discloses the semiconductor device according to claim 1, wherein the trench portion includes a plurality of trench portions, and the transistor section has the plurality of trench portions, and the trench bottom portion is provided to extend from one to an other of the trench portions which are adjacent to each other (transistor section 70 comprises plurality of trench portions with bottom region 17 extending between adjacent trench portions; Figs. 2 and 32; paragraph [0206]).
Regarding claim 3, Naito discloses the semiconductor device according to claim 1, further comprising: a well region of the second conductivity type which is provided in the semiconductor substrate over the edge termination structure section from at least a part of the diode section, wherein an end of the trench bottom portion in a trench array direction is spaced apart from an end of the well region in the trench array direction in a top view (p-type well region 11 in the substrate 10 over edge termination structure within a portion of diode section 80 and having an end that is separated in a direction of the trench portions from the bottom region 17; Figs. 1, 2 and 32; paragraphs [0091]-[0093], [0097]).
Regarding claim 4, Naito discloses the semiconductor device according to claim 2, further comprising: a well region of the second conductivity type which is provided in the semiconductor substrate over the edge termination structure section from at least a part of the diode section, wherein an end of the trench bottom portion in a trench array direction is spaced apart from an end of the well region in the trench array direction in a top view (p-type well region 11 in the substrate 10 over edge termination structure within a portion of diode section 80 and having an end that is separated in a direction of the trench portions from the bottom region 17; Figs. 1, 2 and 32; paragraphs [0091]-[0093], [0097]).
Regarding claim 5, Naito discloses the semiconductor device according to claim 1, wherein the trench bottom portion is electrically floating (bottom region 17 may be electrically floating; Fig. 32; paragraph [0209]).
Regarding claim 6, Naito discloses the semiconductor device according to claim 2, wherein the trench bottom portion is electrically floating (bottom region 17 may be electrically floating; Fig. 32; paragraph [0209]).
Regarding claim 7, Naito discloses the semiconductor device according to claim 1, wherein a doping concentration of the trench bottom portion is larger than a doping concentration of the drift region, and is smaller than a doping concentration of the base region (bottom region 17 may have doping concentration lower than that of base region 14 and higher than that of drift region 18; paragraphs [0105], [0207], [0212]).
Regarding claim 8, Naito discloses the semiconductor device according to claim 2, wherein a doping concentration of the trench bottom portion is larger than a doping concentration of the drift region, and is smaller than a doping concentration of the base region (bottom region 17 may have doping concentration lower than that of base region 14 and higher than that of drift region 18; paragraphs [0105], [0207], [0212]).
Regarding claim 10, Naito discloses the semiconductor device according to claim 1, wherein the trench bottom portion is not provided in the diode section (bottom region 17 not provided in diode section 80; Fig. 32).
Regarding claim 11, Naito discloses the semiconductor device according to claim 2, wherein the trench bottom portion is not provided in the diode section (bottom region 17 not provided in diode section 80; Fig. 32).
Regarding claim 12, Naito discloses the semiconductor device according to claim 1, further comprising: a cathode region of the first conductivity type on a back surface side of the semiconductor substrate in the edge termination structure section (n-type cathode region 82 on back surface of substrate 10 at the end of the active region where edge termination structure is disposed; Fig. 32; paragraph [0099]).
Regarding claim 13, Naito discloses the semiconductor device according to claim 2, further comprising: a cathode region of the first conductivity type on a back surface side of the semiconductor substrate in the edge termination structure section (n-type cathode region 82 on back surface of substrate 10 at the end of the active region where edge termination structure is disposed; Fig. 32; paragraph [0099]).
Regarding claim 14, Naito discloses the semiconductor device according to claim 1, further comprising: an emitter electrode provided above the semiconductor substrate in the active section (emitter electrode 52 disposed above active region; Fig. 2; paragraph [0080]); and a well region of the second conductivity type which is provided in the semiconductor substrate over the edge termination structure section from at least a part of the diode section, wherein the well region is spaced apart from the emitter electrode in the diode section (p-type well region 11 in the substrate 10 over edge termination structure within a portion of diode section 80 and in part being spaced apart from emitter electrode 52 in diode section 80; Figs. 1 and 2; paragraphs [0091]-[0093], [0097]).
Regarding claim 15, Naito discloses the semiconductor device according to claim 2, further comprising: an emitter electrode provided above the semiconductor substrate in the active section (emitter electrode 52 disposed above active region; Fig. 2; paragraph [0080]); and a well region of the second conductivity type which is provided in the semiconductor substrate over the edge termination structure section from at least a part of the diode section, wherein the well region is spaced apart from the emitter electrode in the diode section (p-type well region 11 in the substrate 10 over edge termination structure within a portion of diode section 80 and in part being spaced apart from emitter electrode 52 in diode section 80; Figs. 1 and 2; paragraphs [0091]-[0093], [0097]).
Regarding claim 17, Naito discloses the semiconductor device according to claim 1, wherein the transistor section further has an accumulation region of the first conductivity type which is provided above the trench bottom portion, and the accumulation region is not provided in the diode section (n-type accumulation region 16 provided about region 17 and not in diode section 80; Figs. 2 and 32; paragraph [0103]).
Regarding claim 18, Naito discloses the semiconductor device according to claim 2, wherein the transistor section further has an accumulation region of the first conductivity type which is provided above the trench bottom portion, and the accumulation region is not provided in the diode section (n-type accumulation region 16 provided about region 17 and not in diode section 80; Figs. 2 and 32; paragraph [0103]).
Regarding claim 19, Naito discloses the semiconductor device according to claim 1, wherein the transistor section and the diode section further have an accumulation region of the first conductivity type which is provided above the drift region (transistor section 70 and diode section 80 collectively comprise an n-type accumulation region 16 provided above drift region 18; Figs. 2 and 32; paragraph [0103]).
Regarding claim 20, Naito discloses the semiconductor device according to claim 17, further comprising: the drift region between the accumulation region and the trench bottom portion (portion of drift region 18 under mesa portion 61 and above trench bottom portion is disposed between accumulation region 16 and trench bottom portion; Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Naito in further view of US 2009/0174031 A1 to Wang et al. (hereinafter “Wang”).
Regarding claim 9, Naito discloses the semiconductor device according to claim 7, wherein the doping concentration of the trench bottom portion is 1E14 cm-3 or less.
Naito fails to disclose wherein the doping concentration of the trench bottom portion is 1E12 cm-3 or more and 1E13 cm-3 or less.
However, Wang discloses wherein the doping concentration of the trench bottom portion is 1E12 cm-3 or more and 1E13 cm-3 or less (doping concentration of 1E13 cm-3 at the bottom portion of the trench in substrate 602; Fig. 6; paragraphs [0153], [0206]).
Naito and Wang are both considered to be analogous to the claimed invention because they are in the same field of semiconductor devices with specifically-doped trench bottom portions. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Naito to incorporate the teaching of Wang in order to at least potentially provide enhanced breakdown voltage, reduced leakage current, wider depletion region for better charge control, and lower on-stage voltage drop sensitivity.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Naito.
Regarding claim 16, Naito discloses the semiconductor device according to claim 14, further comprising: an interlayer dielectric film covering the well region in a front surface of the semiconductor substrate (interlayer insulating film 38 disposed over well region 11; Figs. 1, 2 and 38), wherein the interlayer dielectric film is provided over the diode section provided on an outermost side of the active section from the edge termination structure section (film 38 provided over diode section 80 provided on outermost side of active region from edge termination structure portion; Figs. 1-2; paragraph [0079]), a distance between an end of the interlayer dielectric film in the diode section provided on the outermost side of the active section and an end on the diode section side of the well region (distance between end of film 38 in diode section 80 provided on outmost side of active region and end of diode section of well region 11; Fig. 2).
Naito fails to explicitly disclose a distance between an end of the interlayer dielectric film and an end on the diode section side of the well region is 10 µm or more and 30 µm or less.
However, given Naito suggests such an arrangement or similar arrangements, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have modified Naito in this manner in order to at least potentially provide improved electric field distribution and reduced field crowding, enhanced isolation of active regions, mitigation of parasitic capacitance and coupling, and increased robustness against surface contaminants and defects.
Response to Arguments
Applicant's arguments filed December 4, 2025 have been fully considered. Applicant presents substantive amendments to claims 1 and 16 with corresponding arguments. Specifically, Applicant argues that amended claim 1 overcomes the 35 USC 102 rejection using Naito and that amended claim 16 overcomes the 35 USC 112 rejection. Regarding amended claim 1, paragraph [0210] of Naito discloses the bottom region 17 covering at least a part of the bottom portion of the gate trench portion 40 and so Naito discloses amended claim 1. Regarding amended claim 16, the 35 USC 112 rejection has been overcome.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/IAN DEGRASSE/ Examiner, Art Unit 2818
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818