Prosecution Insights
Last updated: August 16, 2026
Application No. 18/305,577

SEMICONDUCTOR DEVICE

Final Rejection §103
Filed
Apr 24, 2023
Priority
Jun 13, 2022 — JP 2022-094823
Examiner
ANGUIANO, MICHAEL
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
2 (Final)
48%
Grant Probability
Moderate
3-4
OA Rounds
3m
Est. Remaining
60%
With Interview

Examiner Intelligence

Grants 48% of resolved cases
48%
Career Allowance Rate
12 granted / 25 resolved
-20.0% vs TC avg
Moderate +12% lift
Without
With
+11.8%
Interview Lift
resolved cases with interview
Typical timeline
3y 6m
Avg Prosecution
35 currently pending
Career history
76
Total Applications
across all art units

Statute-Specific Performance

§103
65.9%
+25.9% vs TC avg
§102
7.1%
-32.9% vs TC avg
§112
26.7%
-13.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 25 resolved cases

Office Action

§103
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Information Disclosure Statement(s) The Information Disclosure Statement(s) filed on April 30, 2026 was considered by the Examiner. Response to Arguments RE: the rejection of claim(s) 1-3, 6-9, 11, 14 under 35 USC 112(b), Applicant’s arguments and/or amendments have been fully considered and resolve the issues of indefiniteness. Accordingly, the rejection of claim(s) 1-3, 6-9, 11, 14 has been withdrawn. RE: the rejection of the claims under 35 USC 103, Applicant’s arguments and/or amendments have been fully considered but are moot in view of the new grounds of rejection presented herein. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3, 6-9, 11, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US20090091899A1 (“Saito”) in view of US20080284007A1 (“Horio”), further in view of US20210225717A1 (“Utsumi”). RE: Claim 1, Saito discloses A semiconductor device (10 in FIGs. 1A-1C), comprising: a semiconductor chip (24, 26 in FIG. 1B); a substrate (18) having the semiconductor chip on a front surface thereof (FIG. 1B shows 24, 26 on front top surface of 18); a case (12) that is rectangular in a plan view of the semiconductor device (FIG. 1A shows 12 is rectangular in a top perspective view; 12 would remain rectangular in a plan view of 24, 26) and includes first to fourth side frames (12B, 12C, 12A, 12D in FIG. 1A) in this order that are attached to the substrate so that the first to fourth side frames are respectively disposed at respective ones of four sides of the substrate to form a housing region therein (internal region defined by 12B, 12C, 12A, 12D; case member 12 having a frame-like shape has four side wall parts in response to four sides of the circuit board 18. To be more specific, the case member 12 is mainly composed of a first side wall part 12A, a second side wall part 12B, a third side wall part 12C, and a fourth side wall part 12D. As for the positions of the respective side wall parts on the sheet, the first side wall part 12A is located at the back, the second side wall part 12B is located in the front, the third side wall part 12C is located to the left, and the fourth side wall part 12D is located to the right, [0031]); and a sealing material (16 in FIGs. 1B-1C, [0029]) filling the housing region to seal the front surface of the substrate and the semiconductor chip, wherein the case has a first attachment portion (12F in FIG. 1C), for attaching a screw thereto, formed at the first side frame(12B; The region surrounded by the inner side wall part 12F is used as a region for fixing the hybrid integrated circuit device 10 by use of a fixing means, such as a screw, [0034]; The region surrounded by the inner side wall part 12F is a region to which the circuit board 18 is to be fixed by a screw, [0057]; lead line for 12F is cutoff in FIG. 1A, however, 12F is better labeled in FIG. 2A), the first attachment portion includes: a pair of first attachment frames (sides of 12F form a pair of first attachment frames of 12F as shown in Annotated FIG. 1A below; By referring to FIGS. 2A, 2B, and 2C, a configuration of the case member 12 used in the above-described hybrid integrated circuit device 10 will be described, [0035]; Accordingly, FIGs. 2A-2C show the case member 12 from FIGs. 1A-1C) extending from the first side frame toward an inside of the housing region, a first connecting frame (first connecting frame of 12F is shown in Annotated FIG. 1A below) connecting ends of the pair of first attachment frames at the inside of the housing region, to thereby form an opening (opening in 12F is shown in Annotated FIG. 1A below, including 28 in FIG. 1C, [0034]) between the first connecting frame and the pair of first attachment frames (FIG. 1C shows 28 defined by 12F; Accordingly, the opening is formed between the first connecting frame of 12F and the pair of first attachment frames of 12F), the opening penetrating through the case in a first direction perpendicular to the front surface of the substrate (FIG. 1C shows the opening in 12F penetrating through the case 12 in a first direction, i.e., vertical direction, perpendicular to the front top surface of the substrate 18), and a first reinforcing portion (30F, 30G labeled in FIGs. 2A, 4B) that is provided in a first region formed by the first side frame and one of the pair of first attachment frames in the plan view (FIG. 4B is a plan view, [0052]), the first reinforcing portion being in contact with the first side frame (FIGs. 2A, 4B show 30F, 30G in contact with 12B), the one of the pair of first attachment frames (FIG. 4B shows 30F, 30G in contact with the sides of 12F which form the pair of first attachment frames), and a first corner (first corner formed by 12B and 12F) at which the first side frame and the one of the pair of first attachment frames are joined in the plan view (Annotated FIG. 4B below shows 30G is in indirect contact, e.g., thermal contact with the first corner formed by the joining of 12B and one of the pair of first attachment frames of 12F). Saito does not explicitly disclose: at least one surface of each of the first attachment frames being parallel to one surface of the second side frame or the fourth side frame in the plan view; the opening being fully exposed to an outside of the housing region in a second direction parallel to the front surface of the substrate and substantially perpendicular to the first side frame. In the same field of endeavor, Horio discloses: at least one surface of each of the first attachment frames being parallel to one surface of the second side frame or the fourth side frame in the plan view (Annotated FIG. 4 shows at least one left side surface of each of the first attachment frames being parallel to the left side surface of a second side frame 20d, and this would remain unchanged in a plan view). Annotated FIG. 4 from Horio below shows resin case 20 includes a pair of first attachment frames extending toward an inside of a housing region with left side surfaces parallel to a second side frame. Annotated FIG. 4 from Horio shows a connecting frame connecting ends of the pair of first attachment frames. Annotated FIG. 4 from Horio shows the pair of first attachment frames and the first connecting frame form a U-shaped structure. Annotated FIG. 4 from Horio shows an opening penetrating the case in a vertical direction. Horio further discloses fastening portions 20 a for bolting are provided on a side portion of the resin case 20 so as to enable installation of the semiconductor module 1 on the cooling member 40. The fastening portions 20 a are integrally molded with the resin case 20, and extend outward from side faces of the resin case 20, [0046]. Additionally, Saito discloses fixing of the circuit board 18 by use of the screw 36 is also carried out inside of an inner side wall part 12E, [0061]. FIG. 2A Saito shows 12F and 12E on opposite sides of the frame are substantially symmetric, with 12E having the same configuration as 12F. Saito further discloses fixing of the circuit board 18 by use of the screw 36 is also carried out inside of an inner side wall part 12E, [0061]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify 12F and 12E to each be a U-shaped structure as taught by Horio as this would provide additional rigidity and structural support to the case 12 in Saito, provide more side protection to the screw 36 when the screw is attached to the case 12 as in FIG. 6 of Saito, and allow the screws to be more accessible on opposite sides of the case 12. Further in the same field of endeavor, Utsumi discloses in FIGs. 1-3: Screwing portions 17 are provided in the frame 15. The screwing portions 17 are notches, two each of which is provided on each of two opposing sides of the frame 15. A screw 18 is passed through the screwing portion 17 to threadedly secure the semiconductor package onto a housing 19, [0021]. FIG. 3 shows the notches are U-shaped and are fully exposed to an outside of a housing region (15) in a second direction (horizontal direction in FIGs. 2-3) parallel to a front surface of a substrate (top surface of 1 in FIG. 2) and substantially perpendicular to the first side frame (left or right side frame of 15 in FIG. 3). In FIG. 6 Saito discloses For attachment of the hybrid integrated circuit device 10 to the heat sink 38, a method by screw fixing by use of a screw 36 is adopted, [0061]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the openings in 12E, 12F to be U-shaped notches as taught by Utsumi in order to simplify future repairs by simplifying the removal of the device 10 from the heat sink 38 in Saito; as the openings are U-shaped and fully exposed in a direction parallel to the top of the substrate 18, instead of removing both screws to uninstall the device 10, only one screw needs to be completely removed and other loosened in order to slide the device 10 along the top of the heat sink and uninstall it during the repair. PNG media_image1.png 690 1212 media_image1.png Greyscale Annotated FIG. 1A of Saito PNG media_image2.png 598 919 media_image2.png Greyscale Annotated FIG. 4B of Saito PNG media_image3.png 615 979 media_image3.png Greyscale Annotated FIG. 4 of Horio RE: Claim 2, Saito in view of Horio discloses The semiconductor device according to claim 1, wherein the first connecting frame has a semicircular shape and projects toward the inside of the housing region in the plan view, such that the opening is of a U-shape in the plan view (As modified by Horio, the first connecting frame would have a semicircular shape and would project toward the inside of the housing region in the plan view; Utsumi FIG. 3 shows the opening/notch is of U-shape in the plan view). RE: Claim 3, Saito in view of Horio discloses The semiconductor device according to claim 2, wherein the first reinforcing portion includes a first reinforcing surface connecting, in the plan view, a first end point and a second end point (Annotated FIG. 4B of Saito below shows the outline of 12F as modified by Horio; In Annotated FIG. 4B below, the surface of 30G connects a first end point and a second end point in the plan view), the first end point being located closest to the inside of the housing region in a portion of the first reinforcing portion that is in contact with the one of the pair of attachment frames (In Annotated FIG. 4B of Saito below shows the first end point in surface of 30G which is closest to the inside of the housing region, and this surface of 30G is in contact with one of the pair of first attachment frames; As modified, 30G would still contact one of the pair of first attachment frames), the second end point being located closest to the second side frame or the fourth side frame in a portion of the first reinforcing portion that is in contact with the first side frame (Annotated FIG. 4B of Saito below shows the second end point closest to 12D in portion of 30G in contact with 12B). PNG media_image4.png 811 1185 media_image4.png Greyscale Annotated FIG. 4B of Saito RE: Claim 6, Saito in view of Horio discloses The semiconductor device according to claim 3, wherein the first reinforcing surface connects the first end point and the second end point in a straight line in the plan view (Annotated FIG. 4B of Saito above for claim 3 shows the side surface of 30G connecting the first end point and second end point in a straight line in the plan view). RE: Claim 7, Saito in view of Horio discloses The semiconductor device according to claim 3, wherein the first end point is located between the first corner and a position at which the one of the pair of first attachment frames and the first connecting frame are connected (Annotated FIG. 4B of Saito above for claim 3 shows the modified outline of 12F and the modified location of the first corner; As modified, the first end point would be located between the first corner and a position at which the one of the pair of first attachment frames and the first connecting frame are connected). RE: Claim 8, Saito in view of Horio discloses The semiconductor device according to claim 3, wherein the first end point is located at a position at which the one of the pair of first attachment frame and the first connecting frame are connected (As claimed, the ends of the first attachment frame and first connecting frame are not limited; Accordingly, as shown in the Annotated FIG. 4B of Saito above for claim 3, the portion of 12F that is directly in contact with 30G is considered to correspond to the claimed one of the pair of first attachment frames; therefore, the first end point is located at the position at which the one of the pair of first attachment frame and the first connecting frame are connected). RE: Claim 9, Saito in view of Horio discloses The semiconductor device according to claim 8, wherein a distance from the first corner to the second end point is in a range of 1 to 1.5 times a distance from the first corner to the first end point (As shown in Annotated FIG. 4B of Saito above for claim 3, the first corner would be formed by the modified outline of 12F and 12B; a circle centered at the first corner is shown in Annotated FIG. 4B of Saito with the first end point and the second end point located at the edge of this circle; Accordingly, the distance from the first corner to the second end point and the distance from the first corner to the first end point would be equal; Alternatively, it has been held where the only difference between the prior art and the claims was a recitation of relative dimensions of the claimed device and a device having the claimed relative dimensions would not perform differently than the prior art device, the claimed device was not patentably distinct from the prior art device. In Gardner v.TEC Syst., Inc., 725 F.2d 1338, 220 USPQ 777, see MPEP 2144.04. In the instant case the prior art device would not perform differently if modified exactly to the claimed dimensions. Therefore the claimed device is not patentably distinct). RE: Claim 11, Saito in view of Horio discloses The semiconductor device according to claim 9, wherein the first side frame is greater in width than the pair of first attachment frames and the first connecting frame (In Saito, FIG. 4B shows vertical width of 12B is greater than vertical width of any portion of 12F). RE: Claim 14, Saito in view of Horio discloses The semiconductor device according to claim 1, wherein the case further includes a second attachment portion (12E in Annotated FIG. 1A of Saito above for claim 1) for attaching another screw thereto (fixing of the circuit board 18 by use of the screw 36 is also carried out inside of an inner side wall part 12E, [0061]), the second attachment portion being at the third side frame (Annotated FIG. 1A of Saito above shows 12E is disposed at the third side frame 12A), and the second attachment portion includes: a pair of second attachment frames (sides of 12E form a pair of second attachment frames of 12E as shown in Annotated FIG. 1A Saito above for claim 1) extending toward the inside of the housing region, at least one surface of each of the second attachment frames being parallel to one surface of the second side frame or the fourth side frame in the plan view (As modified, 12E is a U-shaped structure as 12E was modified above in the same way as 12F; Accordingly, 12E would have at least one side surface of each of its attachment frames parallel to one surface of the second side frame 12C as shown in Annotated FIG. 4 Horio for claim 1 above), a second connecting frame connecting ends of the pair of second attachment frames at the inside of the housing region, to thereby form another opening between the second connecting frame and the pair of second attachment frames (Annotated FIG. 1A of Saito above for claim 1 shows a second connecting frame connecting ends of the pair of second attachment frames at the inside of the housing region, to thereby form another opening between the second connecting frame and the pair of second attachment frames), said another opening penetrating through the case in the first direction perpendicular to the front surface of the substrate, and being fully exposed to the outside of the housing region in a third direction parallel to the front surface of the substrate and substantially perpendicular to the third side frame (As modified, 12E was modified in the same way as 12F; Accordingly, the opening in 12E would penetrate through the case 12 in the first direction, i.e., vertical direction in FIG. 1C Saito, which is perpendicular to the front top surface of the substrate 18, and, being a U-shaped notch, would be fully exposed to the outside of the housing region in a third direction, horizontal direction pointing to the right in FIG. 1C Saito, which is parallel to the front surface of the substrate 18 and substantially perpendicular to the third side frame 12A; Annotated FIG. 1A Saito for claim 1 shows the third direction), and a second reinforcing portion (30B, 30C in FIG. 4B of Saito) that is provided in a second region formed by the third side frame and one of the pair of second attachment frames, the second reinforcing portion being in contact with the third side frame (FIG. 4B of Saito shows 30B, 30C in contact with 12A), the one of the pair of second attachment frames (FIG. 4B shows 30B, 30C in contact with sides of 12E forming the one of the pair of second attachment frames), and a second corner (corner formed at which 12A and12E are joined) at which the third side frame and the one of the pair of second attachment frames are joined in the plan view (FIG. 4B of Saito shows 30B, 30C is in indirect contact, e.g., thermal contact with the corner formed by 12A and 12E). Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL ANGUIANO whose telephone number is (703)756-1226. The examiner can normally be reached Monday through Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at (408) 918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MICHAEL ANGUIANO/Examiner, Art Unit 2899 /DALE E PAGE/Supervisory Patent Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Apr 24, 2023
Application Filed
Dec 31, 2025
Non-Final Rejection mailed — §103
Mar 26, 2026
Response Filed
May 26, 2026
Final Rejection mailed — §103
Jul 22, 2026
Interview Requested
Jul 28, 2026
Applicant Interview (Telephonic)
Jul 28, 2026
Examiner Interview Summary

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12708035
SEMICONDUCTOR MODULE, METHOD OF MANUFACTURING SEMICONDUCTOR MODULE, AND CASE UNIT
3y 9m to grant Granted Aug 11, 2026
Patent 12684807
SEMICONDUCTOR DEVICE, INVERTER CIRCUIT, DRIVE DEVICE, VEHICLE, AND ELEVATOR
3y 10m to grant Granted Jul 14, 2026
Patent 12628642
CIRCUIT STRUCTURE INCLUDING AT LEAST ONE AIR GAP AND METHOD FOR MANUFACTURING THE SAME
3y 2m to grant Granted May 12, 2026
Patent 12564093
SEMICONDUCTOR DEVICE
3y 2m to grant Granted Feb 24, 2026
Patent 12543561
CIRCUIT STRUCTURE INCLUDING AT LEAST ONE AIR GAP AND METHOD FOR MANUFACTURING THE SAME
2y 3m to grant Granted Feb 03, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

3-4
Expected OA Rounds
48%
Grant Probability
60%
With Interview (+11.8%)
3y 6m (~3m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 25 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month