Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Claims 1-12 and newly added claims 21-28 are pending in this application.
Applicant’s election without traverse of Invention I (claims 1-12) in the reply filed on July 20, 2026 is acknowledged. Newly added claims 21-28 also read on the elected invention.
All claims directed to the nonelected invention have been cancelled.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on April 24, 2023 is being considered by the examiner.
Response to Amendment
This Office Action is in response to Applicant’s Amendment filed July 20, 2026. Claims 1-4 and 7-10 are amended. Claims 13-20 are cancelled. Claims 21-28 are newly added. The Examiner notes that claims 1-12 and 21-28 are examined.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 21-22, and 25-28 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0307456 A1 in view of Yu (IEEE Transactions on Nanotechnology, 2019).
With respect to claim 1, Lin teaches in Fig. 2N:
A device comprising:
a stack of nanostructures (nanostructures 106 and 107);
a first plurality of nanosheets (nanostructures 106 which may be nanosheets [0027]) from the stack of nanostructures (106 and 107) having first source and drain regions (116) at opposing ends of each of the first plurality of nanosheets (106) to position first channel regions for a first memory cell;
a second plurality of nanosheets (nanostructures 107) from the stack of nanostructures (106 and 107) having second source and drain regions (117) at opposing ends of each of the second plurality of nanosheets to position second channel regions for a second memory cell;
an isolation liner layer (dielectric layers 128 and 130) between the first source and drain regions (116) and the second source and drain regions (117);
and a shared gate all around (GAA) control gate (gate metal 113) for the first memory cell and the second memory cell, the shared gate all around (GAA) control gate including a tunnel dielectric layer on the first channel regions and the second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.
Lin does not teach that the transistors are used as a memory device and does not teach:
A memory device comprising:
a first plurality of nanosheets (nanostructures 106 which may be nanosheets [0027]) from the stack of nanostructures (106 and 107) having first source and drain regions (116) at opposing ends of each of the first plurality of nanosheets (106) to position first channel regions for a first memory cell;
a second plurality of nanosheets (nanostructures 107) from the stack of nanostructures (106 and 107) having second source and drain regions (117) at opposing ends of each of the second plurality of nanosheets to position second channel regions for a second memory cell;
and a shared gate all around (GAA) control gate (gate metal 113) for the first memory cell and the second memory cell, the shared gate all around (GAA) control gate including a tunnel dielectric layer on the first channel regions and the second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.
Yu teaches that gate all around transistors may be used for NOR flash memory by wrapping the nanostructure with an oxide-nitride-oxide layer. Modifying the transistor architecture of Lin with the gate all around SONOS structure of Yu teaches:
A memory device comprising:
a first plurality of nanosheets (nanostructures 106 of Lin which may be nanosheets [0027]) from the stack of nanostructures (106 and 107) having first source and drain regions (116) at opposing ends of each of the first plurality of nanosheets (106) to position first channel regions for a first memory cell (upper transistor 104, modified by the teachings of Yu to use the transistors of Lin as memory cells);
a second plurality of nanosheets (nanostructures 107) from the stack of nanostructures (106 and 107) having second source and drain regions (117) at opposing ends of each of the second plurality of nanosheets to position second channel regions (lower transistor 105, modified by the teachings of Yu to use the transistors of Lin as memory cells);
and a shared gate all around (GAA) control gate (gate metal 113 of Lin modified to use the SONOS structure of Yu) for the first memory cell (104) and the second memory cell (105), the shared gate all around (GAA) control gate including a tunnel dielectric layer (“thermally grown SiO2 for the tunneling oxide”, Experimental Details of Yu) on the first channel regions and the second channel regions, a trap dielectric layer (“Si3N4 for the charge trap layer,” Experimental Details of Yu) on the tunnel dielectric layer, and a control conductor (113 of Lin, gate of Yu) on the trap dielectric layer (see Fig. 1 of Yu, gate surrounds ONO layer around the nanostructure).
Lin discloses the claimed invention except the stacked transistors do not include the tunnel dielectric, trap dielectric, and blocking dielectric regions and have a different purpose from being a memory device. Yu teaches that it is known to include the oxide-nitride-oxide layers around a nanostructure to make a NOR memory device with a gate all around geometry. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lin as taught by Yu, since Yu states that such a modification would allow the transistors of Lin to be used as a high speed NOR flash memory. See MPEP 2144.
With respect to claim 2, Lin/Yu further teaches:
wherein a first set of electrically conductive structures (conductive layer 124 of Lin) extends from a first end of the memory device (top) to the first memory cell (upper transistor 104 of Lin modified to be a memory cell based on the teachings of Yu).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 3, Lin/Yu further teaches:
wherein a second set of electrically conductive structures (conductive layer 125 of Lin) extends from a second end of the memory device (bottom) to the first memory cell (lower transistor 105 of Lin modified to be a memory cell based on the teachings of Yu).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 4, Yu further teaches:
wherein the shared gate all around (GAA) control gate further comprises a blocking oxide layer (“TEOS for the blocking oxide,” Experimental Details of Yu) between the trap dielectric layer (Si3N4 layer) and the control conductor (gate).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 5, Yu further teaches:
wherein the tunnel dielectric layer is an oxide, and the trap dielectric layer is a nitride. (Experimental Details “The proposed NOR flash memory was fabricated employing a gate-all-around (GAA) structure with a junctionless (JL) silicon nanowire (SiNW) wrapped by oxide-nitride-oxide(O/N/O), which are composed of thermally grown SiO2 for the tunneling oxide, LP-CVD Si3N4 for the charge trap layer, and TEOS for the blocking oxide.”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 6, Yu further teaches:
wherein the memory device is a NOR flash memory device. (Experimental Details “The proposed NOR flash memory was fabricated employing a gate-all-around (GAA) structure with a junctionless (JL) silicon nanowire (SiNW) wrapped by oxide-nitride-oxide(O/N/O), which are composed of thermally grown SiO2 for the tunneling oxide, LP-CVD Si3N4 for the charge trap layer, and TEOS for the blocking oxide.”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 7, Lin teaches in Fig. 2N:
A device comprising:
a stack of nanostructures (nanostructures 106 and 107);
a first plurality of nanowires (nanostructures 106 which may be nanowires [0027]) from the stack of nanostructures (106 and 107) having first source and drain regions (116) at opposing ends of each of the first plurality of nanowires (106) to position first channel regions for a first memory cell;
a second plurality of nanowires (nanostructures 107) from the stack of nanostructures (106 and 107) having second source and drain regions (117) at opposing ends of each of the second plurality of nanowires to position second channel regions for a second memory cell;
an isolation liner layer (dielectric layers 128 and 130) between the first source and drain regions (116) and the second source and drain regions (117);
and a shared gate all around (GAA) control gate (gate metal 113) for the first memory cell and the second memory cell, the shared gate all around (GAA) control gate including a tunnel dielectric layer on the first channel regions and the second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.
Lin does not teach that the transistors are used as a memory device and does not teach:
A memory device comprising:
a first plurality of nanowires from the stack of nanostructures having first source and drain regions at opposing ends of each of the first plurality of nanowires to position first channel regions for a first memory cell;
a second plurality of nanowires from the stack of nanostructures having second source and drain regions at opposing ends of each of the second plurality of nanowires to position second channel regions for a second memory cell;
and a shared gate all around (GAA) control gate for the first memory cell and the second memory cell, the shared gate all around (GAA) control gate including a tunnel dielectric layer on the first channel regions and the second channel regions, a trap dielectric layer on the tunnel dielectric layer, and a control conductor on the trap dielectric layer.
Yu teaches that gate all around transistors may be used for NOR flash memory by wrapping the nanostructure with an oxide-nitride-oxide layer. Modifying the transistor architecture of Lin with the gate all around SONOS structure of Yu teaches:
A memory device comprising:
a first plurality of nanosheets (nanostructures 106 of Lin which may be nanosheets [0027]) from the stack of nanostructures (106 and 107) having first source and drain regions (116) at opposing ends of each of the first plurality of nanosheets (106) to position first channel regions for a first memory cell (upper transistor 104, modified by the teachings of Yu to use the transistors of Lin as memory cells);
a second plurality of nanosheets (nanostructures 107) from the stack of nanostructures (106 and 107) having second source and drain regions (117) at opposing ends of each of the second plurality of nanosheets to position second channel regions (lower transistor 105, modified by the teachings of Yu to use the transistors of Lin as memory cells);
and a shared gate all around (GAA) control gate (gate metal 113 of Lin modified to use the SONOS structure of Yu) for the first memory cell (104) and the second memory cell (105), the shared gate all around (GAA) control gate including a tunnel dielectric layer (“thermally grown SiO2 for the tunneling oxide”, Experimental Details of Yu) on the first channel regions and the second channel regions, a trap dielectric layer (“Si3N4 for the charge trap layer,” Experimental Details of Yu) on the tunnel dielectric layer, and a control conductor (113 of Lin, gate of Yu) on the trap dielectric layer (see Fig. 1 of Yu, gate surrounds ONO layer around the nanostructure).
Lin discloses the claimed invention except the stacked transistors do not include the tunnel dielectric, trap dielectric, and blocking dielectric regions and have a different purpose from being a memory device. Yu teaches that it is known to include the oxide-nitride-oxide layers around a nanostructure to make a NOR memory device with a gate all around geometry. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lin as taught by Yu, since Yu states that such a modification would allow the transistors of Lin to be used as a high speed NOR flash memory. See MPEP 2144.
With respect to claim 8, Lin/Yu further teaches:
wherein a first set of electrically conductive structures (conductive layer 124 of Lin) extends from a first end of the memory device (top) to the first memory cell (upper transistor 104 of Lin modified to be a memory cell based on the teachings of Yu).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 9, Lin/Yu further teaches:
wherein a second set of electrically conductive structures (conductive layer 125 of Lin) extends from a second end of the memory device (bottom) to the first memory cell (lower transistor 105 of Lin modified to be a memory cell based on the teachings of Yu).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 10, Yu further teaches:
wherein the shared gate all around (GAA) control gate further comprises a blocking oxide layer (“TEOS for the blocking oxide,” Experimental Details of Yu) between the trap dielectric layer (Si3N4 layer) and the control conductor (gate).
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 11, Yu further teaches:
wherein the tunnel dielectric layer is an oxide, and the trap dielectric layer is a nitride. (Experimental Details “The proposed NOR flash memory was fabricated employing a gate-all-around (GAA) structure with a junctionless (JL) silicon nanowire(SiNW)wrapped by oxide-nitride-oxide(O/N/O), which are composed of thermally grown SiO2 for the tunneling oxide, LP-CVD Si3N4 for the charge trap layer, and TEOS for the blocking oxide.”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 12, Yu further teaches:
wherein the memory device is a NOR flash memory device. (Experimental Details “The proposed NOR flash memory was fabricated employing a gate-all-around (GAA) structure with a junctionless (JL) silicon nanowire (SiNW) wrapped by oxide-nitride-oxide(O/N/O), which are composed of thermally grown SiO2 for the tunneling oxide, LP-CVD Si3N4 for the charge trap layer, and TEOS for the blocking oxide.”)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 21, Lin in Fig. 2N teaches:
A semiconductor structure comprising:
a stack of nanostructures (nanostructures 106 and 107) comprising:
a first plurality of nanostructures 106 (nanostructures 106) providing first channel regions of a first memory cell;
a second plurality of nanostructures (nanostructures 107) providing second channel regions of a second memory cell;
first source and drain regions (source and drain regions 116) coupled to opposing ends of each of the first plurality of nanostructures (106);
second source and drain regions (source and drain regions 117) coupled to opposing ends of each of the second plurality of nanostructures (107);
an isolation liner layer (dielectric layers 128 and 130) between the first source and drain regions (116) and the second source and drain regions (117);
and a shared gate structure (gate metal 113) surrounding the first channel regions (106) and the second channel regions (107)
Lin does not teach that the transistors are used as a memory device and does not teach:
a first plurality of nanostructures providing first channel regions of a first memory cell;
a second plurality of nanostructures providing second channel regions of a second memory cell;
the shared gate structure comprising:
a tunnel dielectric layer on the first channel regions and the second channel regions;
a trap dielectric layer on the tunnel dielectric layer;
and a control conductor on the trap dielectric layer.
Yu teaches that gate all around transistors may be used for NOR flash memory by wrapping the nanostructure with an oxide-nitride-oxide layer. Modifying the transistor architecture of Lin with the gate all around SONOS structure of Yu teaches:
a first plurality of nanostructures (106) providing first channel regions of a first memory cell (upper transistor 104, modified by the teachings of Yu to use the transistors of Lin as memory cells);
a second plurality of nanostructures (107) providing second channel regions of a second memory cell (lower transistor 105, modified by the teachings of Yu to use the transistors of Lin as memory cells);
the shared gate structure comprising (gate metal 113 of Lin modified to use the SONOS structure of Yu):
a tunnel dielectric layer on the first channel regions and the second channel regions (“thermally grown SiO2 for the tunneling oxide”, Experimental Details of Yu);
a trap dielectric layer on the tunnel dielectric layer (“Si3N4 for the charge trap layer,” Experimental Details of Yu);
and a control conductor on the trap dielectric layer (113 of Lin, gate of Yu).
Lin discloses the claimed invention except the stacked transistors do not include the tunnel dielectric, trap dielectric, and blocking dielectric regions and have a different purpose from being a memory device. Yu teaches that it is known to include the oxide-nitride-oxide layers around a nanostructure to make a NOR memory device with a gate all around geometry. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lin as taught by Yu, since Yu states that such a modification would allow the transistors of Lin to be used as a high speed NOR flash memory. See MPEP 2144.
With respect to claim 22, Yu further teaches:
wherein the shared gate structure further comprises a blocking oxide layer (“TEOS for the blocking oxide,” Experimental Details of Yu) between the trap dielectric layer and the control conductor.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu as explained above.
With respect to claim 25, Lin further teaches:
wherein the first source and drain regions (116) are positioned at a first height within the semiconductor structure,
and wherein the second source and drain regions (117) are positioned at a second height within the semiconductor structure, the second height being different from the first height (see Fig. 2N, 116 and 117 are at different elevations in the z direction).
With respect to claim 26, Lin further teaches:
further comprising inner spacers (inner spacers 114) positioned between the shared gate structure (113) and the first source and drain regions (116) and between the shared gate (113) structure and the second source and drain regions (117), wherein the inner spacers comprise a dielectric material ([0040] “The inner spacers 114 can include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbonitride, fluorine-doped silicate glass (FSG), a low-K dielectric material or other dielectric materials”).
With respect to claim 27, Lin further teaches:
further comprising a first set of electrically conductive structures (conductive layer 124) extending from a first side of the semiconductor structure (top) to the first source and drain regions (116).
With respect to claim 28, Lin further teaches:
further comprising a second set of electrically conductive structures (conductive layer 125) extending from a second side (bottom) of the semiconductor structure to the second source and drain regions (117), wherein the first side and the second side are opposing sides of the semiconductor structure (see Fig. 2N).
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Lin (US 2023/0307456 A1 in view of Yu (IEEE Transactions on Nanotechnology, 2019) as applied to claim 21 above and further in view of Rachmady (US 2023/0073078 A1).
With respect to claim 23, Lin/Yu teaches all limitations of claim 21 upon which claim 23 depends. Lin/Yu fails to teach:
wherein the isolation liner layer has a U-shaped geometry including:
a horizontally orientated portion in direct contact with the first source and drain regions;
and vertically orientated portions extending from the horizontally orientated portion.
Rachmady teaches in Fig. 1a:
wherein the isolation liner layer (isolation structure 111) has a U-shaped geometry including:
a horizontally orientated portion (see annotated Fig. 1a below) in direct contact with the first source and drain regions (source region 113 and drain region 114);
and vertically orientated portions extending from the horizontally orientated portion (see annotated Fig. 1a below).
Lin differs from the claimed invention because the isolation structure of Lin does not have a U-shaped geometry. Rachmady teaches that it is known to use an isolation liner with a U-shaped geometry that has the same function as the liner of Lin of isolating the upper and lower source and drain regions. It would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the U-shaped liner of Rachmady for the rectangular isolation layer of Lin because they are known equivalents and it would have yielded the predictable result of electrically isolating the upper and lower source and drain regions from each other. See KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
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With respect to claim 24, Rachmady further teaches:
wherein each of the second source and drain regions (source region 109 and drain region 110) comprises:
a narrower portion positioned between a respective pair of the vertically orientated portions of the isolation liner layer;
and a wider portion extending laterally beyond the respective pair of the vertically orientated portions. (see annotated Fig. 1a above)
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Lin in view of Yu and Rachmady as explained above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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