DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 24 Apr 2023 for application number 18/305,752. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-20 are presented for examination – claims 1-2, 5-6, 14, and 16-17 are examined herein; non-elected claims 3-4, 7-13, 15, and 18-20 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I. (i.e. Device Embodiment I.) of claims 1-2, 5-6, 14, and 16-17 in the reply filed on 15 Jan 2026 is acknowledged. The traversal is on the ground(s) that, “all identified species share the same fundamental structure…and would be located using the same search strategy”. This is not found persuasive because, as expressed in the Requirement for Restriction filed 12 Jan 2026, the device embodiments are independent/distinct for the reasons stated in the Requirement for Restriction, which creates a serious search and examination burden.
The requirement is still deemed proper and is therefore made FINAL. Further, claim 8 has been withdrawn, as claim 8 is dependent on non-elected claim 7.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-2, 5-6, 14, and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “dummy” such as in “dummy common source line” in claim 1 is used by the claim to specify functional structures (as the structures are electrically connected and constitute a vertical capacitor) while the accepted meaning of “dummy” is of a non-functional structure. The term is indefinite because the specification does not clearly redefine the term. Dependent claims 2, 5-6, 14, and 16 are rejected because they inherit the deficiency.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al. [hereinafter as Kim] (US 2021/0066278 A1).
In reference to claim 17, Kim teaches A non-volatile memory device comprising:
a first chip [second semiconductor layer 400; Fig. 8, para 0083] including a peripheral circuit region [para 0027 discloses circuits on 400]; and
a second chip [first semiconductor layer 300; Fig. 3, para 0083] stacked on the first chip [400], the second chip [300] including a cell region [memory cell array 100; Figs. 2, 8, para 0027],
wherein the second chip [300] includes
a common source line [common source line CSL; Fig. 8, para 0065] having a plate shape [para 0065 discloses CSL is a metal plate], the common source line [CSL] extending in first and second directions [HD1 and HD2; Fig. 8],
first and second dummy common source lines [first and third word line driving signal lines SI1 and SI3; Fig. 8, para 0065] at a same height level [SI1, SI3, and CSL are all at the same height level; Fig. 8] as the common source line [CSL] and electrically isolated from each other [SI1, SI3, and CSL are electrically isolated],
an input/output contact plug [first contact 310; Fig. 8, para 0084] on one side of the common source line [CSL] and extending in a third direction [VD; Fig. 8] perpendicular to the common source line [CSL] to transfer a signal received from an input/output pad [I/O pad; Fig. 8, para 0083] to the first chip [300 and 400 are electrically connected], and
first and second dummy contact plugs [contact CP extending from SI1 and SI3; Fig. 8, para 0064] extending in the third direction [VD; Fig. 8] and connected to the first and second dummy common source lines [SI1 and SI3], respectively, the first and second dummy contact plugs [CP extending from SI1 and SI3] having a same shape as the input/output contact plugs [310 and CP extending from SI1 and SI3 have a particular shape].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 5-6, and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee (US 2022/0130791 A1 – as cited in IDS filed 24 Apr 2023).
In reference to claim 1, Kim teaches A non-volatile memory device comprising:
a first chip [second semiconductor layer 400; Fig. 8, para 0083] having a peripheral circuit [para 0027 discloses circuits on 400] therein; and
a second chip [first semiconductor layer 300; Fig. 3, para 0083] stacked on the first chip [400], the second chip [300] including memory blocks [memory cell array 100; Figs. 2, 8, para 0027],
wherein the second chip [300] includes
a common source line [common source line CSL; Fig. 8, para 0065] having a plate shape [para 0065 discloses CSL is a metal plate], the common source line [CSL] extending in first and second directions [HD1 and HD2; Fig. 8],
first and second dummy common source lines [first and third word line driving signal lines SI1 and SI3; Fig. 8, para 0065] at a same height level [SI1, SI3, and CSL are all at the same height level; Fig. 8] as the common source line [CSL], and
first and second dummy contact plugs [contact CP extending from SI1 and SI3; Fig. 8, para 0064] extending in a third direction [VD; Fig. 8], the first and second dummy contact plugs [contact CP extending from SI1 and SI2] being electrically connected to the first and second dummy common source lines [SI1 and SI3], respectively, and used as electrodes of a vertical capacitor [as voltage is provided to the CPs, a capacitance would exist between the CPs, i.e. the CPs would act as vertical capacitors].
However, Kim does not explicitly teach:
an upper insulating layer covering the common source line and the first and second dummy common source lines.
Kim and Lee teach:
an upper insulating layer [fourth insulating layer 140; Fig. 1A, para 0063 of Lee] covering the common source line [CSL of Kim; analogously, cell source structure CSS; Fig. 1A, para 0064 of Lee] and the first and second dummy common source lines [SI1 and SI3 of Kim; analogously, dummy source structure DSS; Fig. 1A, para 0065 of Lee].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim and Lee before the effective filing date of the claimed invention, to include the insulating layer as disclosed by Lee into the semiconductor device of Kim in order to obtain a semiconductor device with an insulating layer over common source and dummy source structures.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with an insulating layer over common source and dummy source structures to provide the predictable result of managing high voltages, preventing electrical interference, and ensuring structural stability during manufacturing.
In reference to claim 5, Kim and Lee teach the invention of claim 1.
Kim teaches The non-volatile memory device of claim 1, further comprising:
a third dummy common source line [there are a plurality of word line driving signal lines and string selection line driving signal lines; Fig. 8, para 0065] disposed at the same height level as the common source line [CSL]; and
third and fourth dummy contact plugs [CP extending from SS1 and SS2, for example; Fig. 8, para 0065] extending in the third direction [VD] and configured as electrodes of the vertical capacitor [as voltage is provided to the CPs, a capacitance would exist between the CPs, i.e. the CPs would act as vertical capacitors];
the fourth dummy contact plug [one of CP extending from SS1 and SS2, for example] is electrically connected to the third dummy common source line [SS1 or SS2, for example].
Lee teaches wherein the third dummy contact plug is electrically connected to the second dummy common source line [a plurality of dummy plugs DPL may be connected to DSS; Fig. 1A, para 0050].
In reference to claim 6, Kim and Lee teach the invention of claim 5.
Kim and Lee teach The non-volatile memory device of claim 5, further comprising: control logic configured to cause a first voltage to be applied to the second and third dummy contact plugs [a plurality of dummy plugs DPL may be connected to DSS of Lee], and a second voltage different from the first voltage to be applied to the first and fourth dummy contact plugs [CP extending from SI1 and SS1/SS2 of Kim; Fig. 6, paras 0057-0058 of Kim disclose different voltages may be applied to different word lines, i.e. thus the different contact plugs].
In reference to claim 16, Kim and Lee teach the invention of claim 1.
Kim teaches The non-volatile memory device of claim 1, wherein the second chip is inverted and stacked on the first chip [300 is inverted and stacked on 400; Fig. 8, para 0027].
Claim(s) 2 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Lee further in view of Wang et al. [hereinafter as Wang] (US 2023/0062321 A1).
In reference to claim 2, Kim and Lee teach the invention of claim 1.
Kim teaches The non-volatile memory device of claim 1, further comprising:
an input/output contact plug [first contact 310; Fig. 8, para 0084] extending in the third direction [VD ] perpendicular to the common source line [CSL],
wherein the input/output contact plug [310] and the first and second dummy contact plugs [CP extending from SI1 and SI2] have a first shape [310 and CP extending from SI1 and SI3 have a particular shape].
However, Kim and Lee do not explicitly teach:
an input/output pad on the upper insulating layer; and electrically connected to the input/output pad.
Kim, Lee, and Wang teach an input/output pad [pad structures 121-123; Fig. 1, para 0039 of Wang] on the upper insulating layer [insulating layer 601; Fig. 1, para 0040 of Wang; analogously, 140 of Lee]; and an input/output contact plug [310 of Kim] electrically connected to the input/output pad [310 of Kim and 121-123 of Wang would be electrically connected].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Kim, Lee, and Wang before the effective filing date of the claimed invention, to include the input/output pads as disclosed by Wang into the semiconductor device of Kim and Lee in order to obtain a semiconductor device with input/output pads on an insulating layer on source structures.
One of ordinary skill in the art would be motivated to obtain a semiconductor device with input/output pads on an insulating layer on source structures to provide the predictable result of provide electrical isolation and ensure high-yield interconnects.
In reference to claim 14, Kim, Lee, and Wang teach the invention of claim 2.
Kim and Wang teach The non-volatile memory device of claim 2, wherein the first and second dummy common source lines [SI1 and SI3 of Kim] and the first and second dummy contact plugs [CP extending from SI1 and SI3 of Kim] are between the input/output pad [121-123 of Wang] and the common source line [CSL of Kim] in a plane [the structures mentioned in Kim would be between input/output pad of Wang and common source line of Kim, in a plane].
Conclusion
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/ANDREW CHUNG/
Examiner, Art Unit 2898