DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Species I in the reply filed on 1/30/2026 is acknowledged. The traversal is on the grounds that the identified Species are not independent and distinct. This is not found persuasive because the species require a different field of search due to distinct limitations that are required by every species. Furthermore, the Applicant has asserted that all claims are generic and should be examined as a whole. The Examiner respectfully disagrees. Species I should comprise only Claims 1-17.
The requirement is still deemed proper and is therefore made FINAL.
Claims 18-20, 35-36, 39 and 103-106 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 1/30/2026.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-10 & 12-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Martin et al. (US Patent Application Publication # 2019/0181770).
Regarding Claim 1, Martin discloses a power module (i.e. power module 100) comprising:
at least one first switch position device (i.e. upper array of power devices 302 as shown in Fig. 19);
at least one second switch position device (i.e. lower array of power devices 302 as shown in Fig. 19);
a high side Kelvin bus bar (i.e. lower rail 816 connected to the source pad of power device 302 and source kelvin connector terminal 504) configured to transmit Kelvin signals to the at least one first switch position device;
a high side gate bus bar (i.e. upper rail 818 connected to gate wire bond pads) configured to transmit gate signals to the at least one first switch position device;
a low side Kelvin bus bar (i.e. rail 816 connected to the source pad of power device 302 and source kelvin connector terminal 502) configured to transmit Kelvin signals to the at least one second switch position device; and
a low side gate bus bar (i.e. upper rail 818 connected to gate wire bond pads) configured to transmit gate signals to the at least one second switch position device,
wherein the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus bar are configured and arranged such that a high side signal loop inductance and a low side signal loop inductance are substantially equivalent (i.e. the effective current paths are equalized between the power devices 302, such that they each see matched inductances (an equalized, low inductance current path)) (Fig. 4A-5, 10-12A ,17-19, 34-35, 40; Abstract; Paragraphs 0100-0113, 0116-0136, 0156-0163, 0201-0209, 0235-0237).
Regarding Claim 2, Martin discloses that the low side signal loop inductance comprises a low side Kelvin bus bar inductance and a low side gate bus bar inductance combined together with a deduction of a low side mutual inductance; and
wherein the high side signal loop inductance comprises a high side Kelvin bus bar inductance and a high side gate bus bar inductance combined together with a deduction of a high side mutual inductance (Paragraphs 0004-0005, 0059, 0134, 0149, 0252, 0265, 0269).
Regarding Claim 3, Martin discloses that the low side gate bus bar and the low side Kelvin bus bar are arranged with a uniform gap therebetween to reduce the low side signal loop inductance; and
wherein the high side gate bus bar and the high side Kelvin bus bar are arranged with a uniform gap therebetween to reduce the high side signal loop inductance (Fig. 4A-5, 18-19, 34). Rails 816 & 818 are shown to have a uniform gap between them in the drawings.
Regarding Claim 4, Martin discloses that one or more upper surfaces of the low side Kelvin bus bar and the low side gate bus bar are within a same plane to reduce the low side signal loop inductance; and
wherein one or more lower surfaces of the low side Kelvin bus bar and the low side gate bus bar are within a same plane to reduce the low side signal loop inductance (Fig. 4A-5, 18-19, 34; Paragraph 0200). Rails 816 & 818 are shown to be on the same plane in the drawings.
Regarding Claim 5, Martin discloses that one or more upper surfaces of the high side Kelvin bus bar and the high side gate bus bar are arranged in a same plane to lower the low side signal loop inductance; and
wherein one or more lower surfaces of the high side Kelvin bus bar and the high side gate bus bar are arranged in a same plane to lower the low side signal loop inductance (Fig. 4A-5, 18-19, 34; Paragraph 0200). Rails 816 & 818 are shown to be on the same plane in the drawings.
Regarding Claim 6, Martin discloses that one or more upper surfaces of the low side Kelvin bus bar and the low side gate bus bar are within a same plane to reduce the low side signal loop inductance;
wherein one or more lower surfaces of the low side Kelvin bus bar and the low side gate bus bar are within a same plane to reduce the low side signal loop inductance;
wherein one or more upper surfaces of the high side Kelvin bus bar and the high side gate bus bar are arranged in a same plane to lower the high side signal loop inductance; and
wherein one or more lower surfaces of the high side Kelvin bus bar and the high side gate bus bar are arranged in a same plane to lower the high side signal loop inductance (Fig. 4A-5, 18-19, 34; Paragraph 0200). Rails 816 & 818 are shown to be on the same plane in the drawings.
Regarding Claim 7, Martin discloses that a vertical portion (i.e. signal pins of terminal 502) of one of the low side gate bus bar and the low side Kelvin bus bar is laterally adjacent a portion of a lateral portion of the other one of the low side gate bus bar and the low side Kelvin bus bar (Fig. 18, 34; Paragraphs 0111, 0205).
Regarding Claim 8, Martin discloses that a vertical portion (i.e. signal pins of terminal 504) of one of the high side gate bus bar and the high side Kelvin bus bar is laterally adjacent a portion of a lateral portion of the other one of the high side gate bus bar and the high side Kelvin bus bar (Fig. 18, 34; Paragraphs 0111, 0205).
Regarding Claim 9, Martin discloses that at least one of the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus bar comprise an inductance adjustment structure (i.e. resistors 820/822) configured to adjust inductance of the at least one of the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus bar (Fig. 19 & 34; Paragraphs 0158-0163, 0201-0205).
Regarding Claim 10, Martin discloses that at least one of the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus bar comprises at least one lateral portion and at least one longitudinal portion; and
wherein the inductance adjustment structure (i.e. resistors 820/822) comprises a greater vertical height than a vertical height of the at least one lateral portion and the at least one longitudinal portion (Fig. 18-19 & 34; Paragraphs 0158-0163, 0201-0205). Resistors 820/822 are shown at least in Fig. 18 to have a greater vertical height than rails 816 & 818.
Regarding Claim 12, Martin discloses that the low side Kelvin bus bar and the low side gate bus bar are structured and arranged to reduce the low side signal loop inductance to less than 40 nH; and
wherein the high side gate bus bar and the high side Kelvin bus bar are structured and arranged to reduce the high side signal loop inductance to less than 40 nH (Paragraph 0235-0237, 0265, 0267; Claim 13, 26, 55).
Regarding Claim 13, Martin discloses that the low side Kelvin bus bar and the low side gate bus bar are structured and arranged to reduce the low side signal loop inductance to 5 nH - 40 nH; and
wherein the high side gate bus bar and the high side Kelvin bus bar are structured and arranged to reduce the high side signal loop inductance to 5 nH - 40 nH (Paragraph 0235-0237, 0265, 0267; Claim 13, 26, 55).
Regarding Claim 14, Martin discloses a housing (i.e. housing 3502, housing lid 618, housing sidewalls 612, base plate 602), wherein portions of the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus bar are embedded in the housing (Fig. 10, 34-35, 40; Paragraphs 0116, 0128-0132, 0209, 0213, 0248).
Regarding Claim 15, Martin discloses a substrate (i.e. power substrate 606/signal substrate 616), wherein the at least one first switch position device and the at least one second switch position device are arranged on a substrate (Fig. 10, 34-35, 40; Paragraphs 0116, 0119-0125, 0205-0209, 0248).
Regarding Claim 16, Martin discloses that portions of the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus bar are attached to the substrate (i.e. power substrate 606/signal substrate 616) (Fig. 10, 34-35, 40; Paragraphs 0116, 0119-0125, 0205-0209, 0248).
Regarding Claim 17, Martin discloses that the at least one first switch position device and the at least one second switch position device comprise at least one Metal Oxide Field Effect Transistor (MOSFET) and/or diode (Paragraphs 0076, 0135, 0158, 0201).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Martin et al. (US Patent Application Publication # 2019/0181770).
Regarding Claim 11, Martin discloses that the high side Kelvin bus bar, the high side gate bus bar, the low side Kelvin bus bar, and the low side gate bus (i.e. rails 816 & 818) bar each comprise at least one lateral portion and at least one longitudinal portion (Fig. 18-19 & 34; Paragraphs 0158-0163, 0201-0205).
Martin does not explicitly disclose that a vertical dimension of the at least one lateral portion and the at least one longitudinal portion is at least 20% of a power module vertical height.
It would have been an obvious matter of design choice to make a vertical dimension of the at least one lateral portion and the at least one longitudinal portion be at least 20% of a power module vertical height, since such a modification would have involved a mere change in the size of a component. A change in size is generally recognized as being within the level of ordinary skill in the art. In re Rose, 105 USPQ 237 (CCPA 1955). It has also been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It has also been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Relevant Cited Art
The cited art in PTO-892 was found during the examiner's search, but was not relied upon for this office action. However, it is still considered pertinent to the applicant's disclosure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RHADAMES J ALONZO MILLER whose telephone number is (571)270-7829. The examiner can normally be reached Mon-Fri 10am-6pm PST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/RJA/ Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/ Supervisory Patent Examiner, Art Unit 2847
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