Prosecution Insights
Last updated: July 05, 2026
Application No. 18/306,250

SEMICONDUCTOR DEVICE

Non-Final OA §102§112
Filed
Apr 25, 2023
Priority
Jun 08, 2022 — JP 2022-092892
Examiner
MIYOSHI, JESSE Y
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Fuji Electric Co., Ltd.
OA Round
2 (Non-Final)
57%
Grant Probability
Moderate
2-3
OA Rounds
5m
Est. Remaining
76%
With Interview

Examiner Intelligence

Grants 57% of resolved cases
57%
Career Allowance Rate
276 granted / 484 resolved
-11.0% vs TC avg
Strong +19% interview lift
Without
With
+18.7%
Interview Lift
resolved cases with interview
Typical timeline
3y 7m
Avg Prosecution
31 currently pending
Career history
541
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
75.9%
+35.9% vs TC avg
§102
15.8%
-24.2% vs TC avg
§112
5.1%
-34.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 484 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments with respect to claim(s) 1, 2, 6-18 have been considered but are moot in view of the new ground of rejection. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1, 2, 6-18, 20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The specification as filed fails to provide support for the claim limitation of “an area of the second portion of the contact region included in the second transistor region is smaller than an area of the first portion of the contact region included in the first transistor region” as recited at the last 4 lines of claim 1. As can be seen from the elected embodiment of fig. 2, each of the contact regions 15 within region 72 and 73 have the same area, which contradicts what is newly claimed in claim 1. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Mitsuzuka et al. (US PGPub 2020/0335497; hereinafter “Mitsuzuka”). Re claim 19: Mitsuzuka teaches (e.g. figs. 2, 3, and 7 and labeled fig. 7 below) a semiconductor device comprising a semiconductor substrate (10) that has a transistor portion (70) and a diode portion (80) and that is provided with a plurality of trench portions (30, 40), wherein the semiconductor substrate (10) has: a drift region (drift region 18; e.g. paragraph 83) of a first conductivity type (n-type); a base region (base region 14; e.g. paragraph 61) of a second conductivity type (p-type) provided above the drift region (18); an emitter region (N+ emitter 12; e.g. paragraph 61) of the first conductivity type (n-type) which is provided above the base region (14) and which has a doping concentration higher (N+ emitter 12 has higher concentration than n- drift region 18) than that of the drift region (18); and a contact region (regions CR1 and CR2) of the second conductivity type (P+ contact areas 15) which is provided above the base region (14) and which has a doping concentration higher (P+ regions 15 have higher concentrations than P-regions of base 14) than that of the base region (14), the transistor portion (70) has: a first transistor region (region of 70 labeled R1) which includes a plurality of first portions of the contact region (CR1); and a second transistor region (region of 70 labeled R2) a plurality of second portions of the contact region (CR2) which is provided between the first transistor region (1R) and the diode portion (80), an area of the emitter region (ER2) in the second transistor region (R2) is larger than an area of the emitter region (ER1) in the first transistor region (R1), and in an extension direction (up-down direction of fig. 7) of the plurality of trench portions (30, 40), a length of each of the plurality of first portions of the contact region (CR1) included in the first transistor region (R1) is equal (there exists a length within CR1 which is equal to a length within CR2) to a length of each of the plurality of second portions of the contact region (CR2) included in the second transistor region (R2), and a number of the plurality of second portions of the contact region (CR2) included in the second transistor region (R2) is smaller (the region R1 has many more cells not drawn and would contain many more regions CR1 than there are in the one row of CR2 in R2) than a number of the plurality of first portions of the contact region (CR1) included in the first transistor region (R1). PNG media_image1.png 582 578 media_image1.png Greyscale Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JESSE Y MIYOSHI/ Primary Examiner, Art Unit 2898
Read full office action

Prosecution Timeline

Apr 25, 2023
Application Filed
Dec 04, 2025
Non-Final Rejection mailed — §102, §112
Feb 26, 2026
Response Filed
Apr 28, 2026
Final Rejection mailed — §102, §112
Jun 22, 2026
Response after Non-Final Action

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

2-3
Expected OA Rounds
57%
Grant Probability
76%
With Interview (+18.7%)
3y 7m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 484 resolved cases by this examiner. Grant probability derived from career allowance rate.

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