DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1,3,6,11-12 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ho et al. (US 2016/0172436 A1, hereinafter Ho ‘436).
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With respect to Claim 1 Ho ‘436 discloses a manufacturing method of a semiconductor structure (Fig 1A-1F), comprising:
providing a substrate (100, Fig 1C, Para [0034]), wherein the substrate (100) comprises a region (102, Fig 1C, Para ) of a first conductivity type (first type, n-type, disclosed in Para [0034]);
forming a patterned photoresist layer (patterned photoresist of 106, Fig 1C and in dashed region of annotated Fig 1 C of Ho ‘436, Para [0037], hereinafter PPL) above the substrate (100), wherein the patterned photoresist layer (PPL) comprises a main portion (main portion as shown in annotated Fig 1C of Ho ‘436, Para [0037], hereinafter MP) and a split portion (split portion as shown in annotated Fig 1C of Ho ‘436, Para [0037], hereinafter SP) separated from each other (as shown on annotated Fig 1C of Ho ‘436);
performing an ion implantation process (108, Fig 1C, Para [0038]) on the substrate (100) by using the patterned photoresist layer (PPL) as a mask (disclosed in Para [0038]) to form a well region (110-4, Fig 1C, Para [0038]) in the region of the first conductivity type (102)(wells formed in 102 shown in Fig 1C), wherein the well region (110-4) has a second conductivity type (second type, p-type, disclosed in Para [0038]), and the main portion (MP) and the split portion (SP) are adjacent to the same end terminal of the well region (110-4)(MP and SP adjacent to the same end terminal of 110-4 shown in annotated Fig 1C of Ho ‘436); and
forming an isolation structure (104, Fig 1C, Para [0035]) in the substrate (100), wherein
the split portion (SP) is located directly above (SP directly above 110-4 shown in annotated Fig 1C of Ho ‘436) the well region (110-4), and
the split portion (SP) is located directly above (SP directly above 104 shown in annotated Fig 1C of Ho ‘436) the isolation structure (104).
With respect to Claim 3 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 further discloses wherein the first conductivity type is an N-type conductivity type (first type, n-type, disclosed in Para [0034]), and the second conductivity type is a P-type conductivity type (second type, p-type, disclosed in Para [0038]).
With respect to Claim 4 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 discloses further wherein the split portion (SP) is a terminal portion of the patterned photoresist layer (PPL)(annotated Fig 1C of Ho ‘436 discloses that SP is the terminal portion of the patterned photoresist layer PPL).
With respect to Claim 6 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 further discloses wherein a width of the main portion is greater than a width of the split portion (annotated Fig 1C of Ho ‘436 discloses the width of the main portion is greater than a width of the split portion).
With respect to Claim 11 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 discloses further comprising: removing the patterned photoresist layer (PPL, as disclosed in Para [0038]); and performing a heating process (disclosed in Para [0039], after removal of PPL) on the substrate (100).
With respect to Claim 12 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 11, and Ho ‘436 discloses further wherein the heating process (disclosed in Para [0039]) comprises an anneal process (annealing process disclosed in Para [0039]).
With respect to Claim 18 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 further discloses wherein a part (SP) of the patterned photoresist layer (PPL) is positioned on (annotated Fig 1C of Ho ‘436 discloses SP positioned on 104) the isolation structure (104).
With respect to Claim 19 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 discloses further wherein the patterned photoresist layer (PPL) exposes a part of the isolation structure (104)(Fig 1C and Para [0037] discloses PPL exposes a part of isolation structure 104).
With respect to Claim 20 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 discloses further wherein a part of the well region (region 110-4) is positioned directly under the isolation structure (104)(Fig 1C discloses 110-4 positioned directly under isolation structure 104).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Ho ‘436 in view of the following arguments.
With respect to Claim 2 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and in a further embodiment Ho ‘436 further discloses wherein the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type (Para [0013 and 0051] discloses an embodiment where “the first conductivity type is P type and the second conductivity type is N-type”).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Ho ‘436’s further teaching of the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type into Ho ‘436’s method. Both methods taught by Ho ‘436 teach the creation of PN junctions to reduce the possibility of breakdown voltage (Para [0006]). One of ordinary skill in the art would recognize that changing the conductivity types of respective PN junction regions is a well-known method. The ordinary artisan, therefore, would have been motivated to modify Ho ‘436 in the manner set forth above, at least, because having methods that enable PN first and second conductivity types to be created as either p-type of n-type in forming PN junctions would create additional potential uses for the end device.
As incorporated, having the first conductivity type is a P-type conductivity type, and the second conductivity type is an N-type conductivity type as further taught by Ho ‘436 would be used in the method of Ho ‘436.
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Ho ‘436 in view of Lee et al. (US 2018/0040651 A1, hereinafter Lee ‘651), in view of the following arguments.
With respect to Claim 7 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, but Ho ‘436 fails to explicitly disclose wherein a width of the split portion is 0.05 µm to 2 µm.
Nevertheless, in a related endeavor, (Fig 1 of Lee ‘651), Lee ‘651 teaches wherein a width (W2, Fig 1 of Lee ‘651, Para [0026]) of the split portion (split portion of 114, Fig 1 of Lee ‘651, Para [0026]) is 0.05 μm to 2 μm (Para [0026] of Lee ‘651 discloses W2 as 60nm (0.06µm)).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Lee ‘651’s teaching of a width of the split portion is 0.05 μm to 2 μm into Ho’436’s method. Ho ‘436 teaches a method to create a pn junction in a transistor to create regions to control breakdown voltage and presents a photoresist with relative sizes of resist between openings but is silent on the dimensions for those resist regions. A person of ordinary skill in the art would be motivated then to use the photoresist dimensions of Lee ‘651 to create a pn junction, as Lee ‘651 teaches in Para [0004] the method of creating the pn junction reduces crosstalk (reduction of parasitic capacitance or conductive coupling) in the device.
As incorporated, the method wherein a width of the split portion is 0.05 μm to 2 μm as taught by Lee ‘651 would be used in the method of Ho ‘436 as the width of the split portion (SP).
With respect to Claim 8 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, but Ho ‘436 fails to explicitly disclose wherein a width of the split portion is 0.2 µm to 1 µm.
Nevertheless, in a related endeavor, (Fig 1 of Lee ‘651), Lee ‘651 teaches wherein a width (W2, Fig 1 of Lee ‘651, Para [0026]) of the split portion (split portion of 114, Fig 1 of Lee ‘651, Para [0026]).
Lee ‘651 fails to expressly disclose wherein a width of the split portion is 0.2 μm to 1 μm. However, the examiner notes that in the applicants disclosure teaches wherein the recited width of the split portion has the advantage of creating a pn junction with increased breakdown voltage. Having this mind, Lee ‘651 teaches wherein a width (W2, Fig 1 of Lee ‘651, Para [0026]) of the split portion (split portion of 114, Fig 1 of Lee ‘651, Para [0026]) is 0.05 μm to 2 μm (Para [0026] of Lee ‘651 discloses W2 as 60nm (0.06µm)). Therefore, it would have been obvious to a person of ordinary skill in the art to arrive at the recited limitation through routine optimization, to obtain the well-known advantage of creating a pn junction using a split region of the photoresist with a width of 0.2 μm to 1 μm to achieve a pn junction with an increased breakdown voltage. See MPEP§2144.05 (II)(A),(B).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Ho ‘436 in view of in view of Baars et al. (US 8,513,083 B2, hereinafter Baars ‘083), in view of the following arguments.
With respect to Claim 9 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, but Ho ‘436 fails to explicitly disclose wherein a spacing between the main portion and the split portion is 0.05 µm to 2µm.
Nevertheless, in a related endeavor (Fig 1A of Baars ‘083), Baars ‘083 teaches wherein a spacing (43, Fig 1A of Baars ‘083, Col 2, Lines 21-24) between the main portion (260 on rightmost side of device shown in Fig 3A of Baars ‘083) and the split portion (center portion of 260 as shown in Fig 3A of Baars ‘083) is 0.05 μm to 2 μm (Col 2, Lines 21-24 of Baars ‘083 discloses spacing 43 as 0.5µm. Note Col 2, Lines 33-35 discloses a mask, that is not shown, used during the ion implantation step).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Baars ‘083’s teaching of a spacing between the main portion and the split portion is 0.05 μm to 2 μm into Ho ‘436’s method. Ho ‘436 teaches a method to use a photoresist to perform ion implantation over a well region in a transistor and presents a photoresist with relative sizes of spacings but does not provide dimensions for those spacings. A person of ordinary skill in the art would be motivated then to use the photoresist spacing dimensions of Baars ‘083 to create a photoresist to perform ion implantation over a well region as Baars ‘083 teaches a proven method and recites specific photoresist dimensions that a person of ordinary skill in the art can use in their method thereby reducing the amount of R&D process work required to determine appropriate dimensions for the split structure of the photoresist, saving development costs.
As incorporated, the teaching of the spacing between the main portion and the split portion method as taught by Baars ‘083 would be used in the method of Ho ‘436 as the spacing between the photoresist split portion (SP) and main portion (MP).
With respect to Claim 10 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, but Ho ‘436 fails to explicitly disclose wherein a spacing between the main portion and the split portion is 0.2 µm to 1 µm.
Nevertheless, in a related endeavor (Fig 1A of Baars ‘083), Baars ‘083 teaches wherein a spacing (43, Fig 1A of Baars ‘083, Col 2, Lines 21-24) between the main portion (260 on rightmost side of device shown in Fig 3A of Baars ‘083) and the split portion (center portion of 260 as shown in Fig 3A of Baars ‘083) is 0.2 μm to 1 μm (Col 2, Lines 21-24 of Baars ‘083 discloses spacing 43 as 0.5µm. Note Col 2, Lines 33-35 discloses a mask, that is not shown, used during the ion implantation step).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Baars ‘083’s teaching of a spacing between the main portion and the split portion is 0.2 μm to 1 μm into Ho ‘436’s method. Ho ‘436 teaches a method to use a photoresist to perform ion implantation over a well region in a transistor and presents a photoresist with relative sizes of spacings but does not provide dimensions for those spacings. A person of ordinary skill in the art would be motivated then to use the photoresist spacing dimensions of Baars ‘083 to create a photoresist to perform ion implantation over a well region as Baars ‘083 teaches a proven method and recites specific photoresist dimensions that a person of ordinary skill in the art can use in their method thereby reducing the amount of R&D process work required to determine appropriate dimensions for the split structure of the photoresist, saving development costs.
As incorporated, the teaching of the spacing between the main portion and the split portion method as taught by Baars ‘083 would be used in the method of Ho ‘436 as the spacing between the photoresist split portion (SP) and main portion (MP).
Claims 13-16 are rejected under 35 U.S.C. 103 as being unpatentable over Ho ‘436 in view of Hikasa (US 2017/0288026 A1, hereinafter Hikasa ‘026), in view of the following arguments.
With respect to Claim 13 Ho ‘436 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 1, and Ho ‘436 fails to explicitly disclose further comprising: forming a dielectric layer on the substrate.
Nevertheless, in a related endeavor (Fig 8A-8F of Hikasa ‘026), Hikasa ‘026 teaches forming a dielectric layer (12, Fig 8A of Hikasa ‘026, Para [0082]) on the substrate (substrate of 2, Fig 8A of Hikasa ‘026, Para [0082]).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hikasa ‘026’s teaching of forming a dielectric layer on the substrate into Ho ‘436’s method. A person of ordinary skill in the art would be motivated to include forming a dielectric layer on the substrate process of Ho ‘436, as the dielectric layer on the substrate would provide some protection for the structure of the substrate from damage during the manufacturing process and it provides a layer to inhibit the migration of the ions from the doped areas of the substrate into structures that may be above them.
As incorporated, the teaching of forming a dielectric layer as taught by Hikasa ‘026 would be used on the substrate (100) in the method of Ho ‘436.
With respect to Claim 14 Ho ‘436 as modified by Hikasa ‘026 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 13, and in an embodiment Hikasa ‘026 further discloses wherein a part of the patterned photoresist layer (15, Fig 8B of Hikasa ‘026, Para [0083]) is positioned on the dielectric layer (12)(Fig 8B of Hikasa ‘026 discloses a part of layer 15 over layer 12).
Therefore, it would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Hikasa ‘026’s further teaching of a part of the patterned photoresist layer positioned on the dielectric layer into Ho ‘436 as modified by Hikasa ‘026’s method. A person of ordinary skill in the art would be motivated to have a part of the patterned photoresist layer positioned on the dielectric layer as photoresist layer enables the ions of the ion implementation process to be directed and the dielectric layer under the photoresist layer protects the substrate and well region from interaction from the photoresist and protect that area from damage during the eventual removal of the photoresist.
As incorporated, the teaching of positioning a part of the patterned photoresist layer over the dielectric layer as taught by Hikasa ‘026 would be used in forming the patterned photoresist (PPL of Ho ‘436) over the dielectric layer (12 of Hikasa ‘026 as incorporated above) in the method of Ho ‘436 as modified by Hikasa ‘026.
With respect to Claim 15 Ho ‘436 as modified by Hikasa ‘026 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 13, and Hikasa ‘026 further discloses wherein the patterned photoresist layer (15) exposes a part of the dielectric layer (12)(Fig 8B of Hikasa ‘026 discloses a part of layer 12 exposed by layer 15).
With respect to Claim 16 Ho ‘436 as modified by Hikasa ‘026 discloses all limitations of the manufacturing method of the semiconductor structure according to claim 13, and Hikasa ‘026 further discloses wherein a forming method of the dielectric layer (12) comprises a thermal oxidation method (Para [0082] of Hikasa ‘026 discloses layer 12 formed by thermal oxidation).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PAUL A. BERRY whose telephone number is (703)756-5637. The examiner can normally be reached M-F 8-5 EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Maldonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/PAUL A BERRY/Examiner, Art Unit 2898 /JULIO J MALDONADO/Supervisory Patent Examiner, Art Unit 2898