DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 13 is objected to because of the following informalities:
In Claim 13, line 1, the recitation of “the digital circuit an XOR gate” should change to read as ---the digital circuit comprises an XOR gate---. Appropriate correction is required.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground rejection.
The independent claim 1 has been newly added limitations which has not been examined on its merits in the previous office, the applicant’s arguments with respect to claim has been considered but is moot because the new ground of rejection.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5 & 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cowles et al. (US 7,924,067 B2, hereinafter called Cowles).
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Regarding claim 1:
Cowles discloses in annotated Fig. 6, a structure comprising:
a first differential amplifier (624) coupled to an input line (annotated LineA), a reference line (annotated LineB) and a first output line (LO1), wherein the first differential amplifier has a first input offset; and
a second differential amplifier (620) coupled to the input line (LineA), the reference line, and a second output line (LO2), wherein the second differential amplifier includes a second input offset in a different direction from the first input offset,
wherein each differential amplifier includes a pair of transistors (differential amplifier 624 includes transistors M5 & M6 and differential amplifier 620 includes transistors M7 & M8),
each pair of transistors being coupled to a respective pair of amplifier transistors having gates coupled to each other (transistor pair M5 and M6 having gate terminals connected to each other; transistor pair M7 & M8 having gate terminals connected to each other); and to a node (annotated N1) between one of the transistors (e.g. M5) and one (M1) of the amplifier transistors.
Regarding claim 4:
Cowles discloses in annotated Fig. 6, wherein the first differential amplifier (624) and the second differential amplifier (620) are free of resistive couplings to the reference line (Fig. 6, none resistive element being connected to VREF line).
Regarding claim 5:
Cowles discloses in annotated Fig. 6, wherein a magnitude of the first input offset is substantially equal to a magnitude of the second input offset (Fig. 6 of Cowles discloses same input line (annotated LineA) connected to the input of each differential amplifiers (634 & 620), see Abstract, The combination of N and P-channel differential pairs results in symmetry across a wide range of reference and supply voltages).
Regarding claim 7:
Cowles discloses in annotated Fig. 6, wherein the first differential amplifier (634) and the second differential amplifier (620) are within a window comparator circuit (the output signal is provided by comparing input signal (VIN) and reference voltage (VREF).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Cowles in view of McEldowney (US 6140872 A).
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Regarding claim 2:
Cowles discloses in annotated Fig. 6, a structure (differential amplifier) comprising the limitations as applied in claim 1.
Cowles does not disclose a first pair of asymmetrically sized transistors within the first differential amplifier and a second pair of asymmetrically sized transistors within the second differential amplifier.
McEldowney discloses in Fig. 1A an amplifier circuit comprising a differential amplifier includes transistors 17 & 18, wherein the transistor 17 having channel-width-to-channel-length ratio (i.e., the W/L ratio, W/L = 2 large) and the transistor 18 having W/L=1, small and a differential amplifier in includes transistors (19 & 20) wherein
wherein the transistor 19 having channel-width-to-channel-length ratio (i.e., the W/L ratio, W/L +1 is appear to be typos, should be “W/L =1”, hereinafter called W/L =1, small) and the transistor 20 having W/L=2, large.
Accordingly, it would have been obvious in view of the reference, taken as a whole, to have modified the circuit of Cowles to have a first pair of asymmetrically sized transistors within the first differential amplifier and a second pair of asymmetrically sized transistors within the second differential amplifier as taught by McEldowney. Such a modification would have imparted the advantageous benefit of improving correction signal into a differential amplifying stage and offset compensation (Col. 2, lines 7-8, n improved technique for inputting a correction signal into a differential amplifying stage and Col. 5, lines 33-35, the pairs of asymmetrical input transistors 17, 18 and 19, 20 contribute to improved offset compensation), thereby suggesting the obviousness of such a modification.
Accordingly, as an obvious consequence above, the combination (Cowles in view of McEldowney) further discloses the first pair of asymmetrically sized transistors (Fig. 1A of McEldowney, transistors 17 & 18) within the first differential amplifier configured to define the first input offset, wherein the input line (Fig. 6 of Cowles, LineA) is coupled to a larger size transistor (transistor 17, W/L = 2, larger) and the reference line (LineB) is coupled to a smaller size transistor (transistor 18, W/L =1) of the first pair of asymmetrically sized transistors; and
a second pair of asymmetrically sized transistors (Fig. 1A of McEldowney, transistors 19 & 20) within the second differential amplifier configured to define the second input offset, wherein the input line (LineA) is coupled to a smaller size transistor (transistor 19, W/L = 1) and the reference line is coupled to a larger size transistor (transistors 20, W/L = 2 of the second pair of asymmetrically sized transistors.
Allowable Subject Matter
Claims 3 & 6 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 3 & 6 are allowable since the closest prior art (i.e. Cowles) does not disclose wherein the first differential amplifier and the second differential amplifier each include a pair of asymmetrically sized resistors configured to define the first input offset or the second input offset; and further comprising an XOR gate coupled to the first output line and the second output line.
Claims 8-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Independent claim 8 is allowable since the closest prior art (i.e., Cowles of record) does not teaches the limitation of “digital circuit coupled to the first output line and the second output line, wherein the digital circuit is configured to indicate whether a voltage in the input line is lower than a difference between the reference voltage and the first input offset or greater than a sum of the reference voltage and the second input offset” in Claim 8 and “determining, based on an output from the first differential amplifier and an output from the second differential amplifier, whether the input signal is lower than a difference between the reference voltage and the first input offset or greater than a sum of the reference voltage and the second input offset” in Claim 15. As such, the combination of limitations of the independent claims 8 & 15 overcome the prior art.
Claims 9-14 & 16-20 are allowable as being dependent of claims 8 & 15, respectively
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/KHIEM D NGUYEN/Examiner, Art Unit 2843
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