DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9.9.2026 has been entered.
Election/Restrictions
Claims 6-8 and 19 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected invention/species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 9.3.2025.
Claim Rejections - USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (of record, US 20230014468 A1) in view of Ho et al. (US 10121882 B1)
Regarding claim 1, Park discloses a gate-all-around (GAA) field-effect transistor (FET) device (Figs. 1 and 2A-2C), comprising:
a semiconductor substrate (101);
a P-type semiconductor material (P) (P-type) diffusion region (AF3/W2, “p-type well W2”) in the semiconductor substrate;
an N-type semiconductor material (N) (N-type) diffusion region (AF1/W1, “n-type well W1”) in the semiconductor substrate;
a gate (145+155) adjacent to the semiconductor substrate and extending in a first direction (Y, Fig. 1), the gate comprising:
a first active gate region (145 over AF3/W2) in the P-type diffusion region;
a second active gate region (145 over AF1/W1) in the N-type diffusion region; and
a plurality of inactive gate regions (155) each outside of the P-type diffusion region and outside of the N-type diffusion region (Fig. 1);
a GAA NFET (“p-type well W2 for an N-MOS transistor”) disposed in the P-type diffusion region, the GAA NFET comprising:
an N-type channel (CH2) extending (partly at least) in a second direction (X) orthogonal to the first direction (Y), the N-type channel adjacent to a first inactive gate region (155 next to it) of the plurality of inactive gate regions (Fig. 2A); and
a first active gate (145) comprising at least a portion of the first active gate region of the gate surrounding the N-type channel (Fig. 2A);
a GAA PFET (“n-type well W1 for a P-MOS transistor”) disposed in the N-type diffusion region, the GAA PFET comprising:
a P-type channel (CH1) extending (partly at least) in the second direction (X), the P-type channel adjacent to a second inactive gate region (155 next to it) of the plurality of inactive gate regions (Fig. 2A); and
a second active gate (145) comprising at least a portion of the second active gate region of the gate surrounding the P-type channel (Fig. 2A); and
a strain material of a first strain type disposed in the first inactive gate region and the second inactive gate region (155, “the gate isolation pattern 155 may include silicon nitride”; silicon nitride is the material disclosed by applicant at, e.g., claim 4 or [0039] of the published application – “the strain material 222(1)-222(3) could be Silicon Nitride (SiN)”), wherein the strain material (155, SiN) extends (towards thereof) outside each of the plurality of inactive gate regions in the second direction (X, Fig.1. In X direction, each of 155 extends towards the outside of each 155).
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Park fails to disclose wherein the strain material extends “beyond an” outside of each of the plurality of inactive gate regions in the second direction.
Ho discloses (Fig. 27B) wherein the strain material (2762) extends beyond an outside an inactive gate region (part of gate outside of fins 2752 and 2754) in the second direction (2753).
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It would have been obvious to one of ordinary skill in the art, before the effective filing date, to include the arrangement of Ho in Park and arrive at wherein the strain material extends “beyond an” outside of each of the plurality of inactive gate regions in the second direction as claimed so as to electrically disconnect sections of a gate while allowing for continuous contact placement across multiple fins and/or because it has been held that a change in size/shape is generally recognized as being within the level of ordinary skill in the art. See MPEP 2144.04 IV.
Regarding claim 2, Park/Ho discloses the GAA FET device of claim 1, wherein:
the strain material (SiN) is configured to (MPEP 2111, 2112 and/or 2114) apply a first strain of the first strain type on the N-type channel (CH2) in the first direction (Y. The claimed property is presumed met by Park since SiN is disclosed by the applicant and by Park and no additional structural limitations are claimed); and
the strain material (SiN) is configured to (MPEP 2111, 2112 and/or 2114) apply a second strain of the first strain type on the P type channel (CH1) in the first direction (Y. The claimed property is presumed met by Park since SiN is disclosed by the applicant and by Park and no additional structural limitations are claimed).
Regarding claim 3, Park/Ho discloses the GAA FET device of claim 1, wherein the first strain type is a tensile strain (Park discloses SiN which matches that of applicant at claim 4 or [0039] of the published application – “the strain material 222(1)-222(3) could be Silicon Nitride (SiN)”; hence, Park discloses the tensile strain as an inherent property of the material used which is the same in Park and the instant application. See MPEP 2111, 2112 and/or 2114).
Regarding claim 4, Park/Ho discloses the GAA FET device of claim 1, wherein the strain material comprises silicon nitride (SiN) (“the gate isolation pattern 155 may include silicon nitride”).
Regarding claim 5, Park/Ho discloses the GAA FET device of claim 1, wherein the plurality of inactive gate regions (155) further comprise a common inactive gate region (middle 155 in Fig. 2A) between the N-type diffusion region and the P type diffusion region in the first direction (Y, Fig. 2A).
Regarding claim 16, Park/Ho discloses the GAA FET device of claim 1, wherein:
the strain material (155, SiN) extends parallel to a least one of the N-type channel and the P-type channel (CH1/CH2) in a third direction (Z) orthogonal to the first direction (Y) and the second direction (X, Fig. 2A).
Regarding claim 18, Park/Ho discloses the GAA FET device of claim 1, wherein the P-type diffusion region (W2/AF3) is between the first inactive gate region (rightmost 155; Fig. 2A) and the N-type diffusion region (AF1/W1) in the first direction (Y, Fig. 2A).
Regarding claim 20, Park/Ho discloses the GAA FET device of claim 1, wherein the N-type diffusion region (AF1/W1) is between the second inactive gate region (leftmost 155) and the P-type diffusion region (W2/AF3) in the first direction (Y, Fig. 2A).
Response to Arguments
Applicant's arguments filed 9.9.2026 have been fully considered but they are not persuasive.
Applicant alleges the prior art of record fails to disclose or suggest wherein the strain material extends beyond an outside of each of the plurality of inactive gate regions in the second direction; the examiner introduces Ho et al. to cover this deficiency in Park et al. See rejection above for details.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDRES MUNOZ whose telephone number is (571)270-3346. The examiner can normally be reached 8AM-5PM Central Time.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571)270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Andres Munoz/Primary Examiner, Art Unit 2818
