Listed by the USPTO as MUNOZ, ANDRES F
Tech Center 2800 • Art Units: 2818 2848 2894 2897
This examiner grants 76% of resolved cases
MUNOZ, ANDRES F is assigned to Tech Center 2800 and art unit 2818. The profile covers 728 resolved cases, with a 76.5% allowance rate. The median time to allowance is 817 days. Interviews are associated with a 17.3% lift in the reported allowance outcome.
The listed company activity includes Intel Corporation, Taiwan Semiconductor Manufacturing Company, Ltd., and Samsung Electronics Co., Ltd. The principal firms are FISH & RICHARDSON P.C. (TC), SCHWABE, WILLIAMSON & WYATT, P.C., and Akona IP PC - Intel. Applicants in this docket may benefit from preparing interview strategy alongside claim amendments, while allowing for the recorded prosecution duration.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 18731878 | SEMICONDUCTOR DEVICE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18680492 | SEMICONDUCTOR DEVICE | Non-Final OA | Samsung Electronics Co., Ltd. |
| 17872139 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 18495975 | DISPLAY DEVICE AND METHOD OF MANUFACTURING THE SAME | Non-Final OA | Samsung Display Co., LTD. |
| 18306421 | GATE-ALL-AROUND (GAA) FIELD-EFFECT TRANSISTOR (FET) DEVICE EMPLOYING STRAIN MATERIAL IN INACTIVE GATE REGION(S) FOR APPLYING CHANNEL STRAIN FOR INCREASED CARRIER MOBILITY, AND RELATED FABRICATION METHODS | Non-Final OA | QUALCOMM Incorporated |
| 19033078 | INTEGRATED CIRCUIT PACKAGE HAVING WIREBONDED MULTI-DIE STACK | Non-Final OA | Intel Corporation |
| 18601774 | PACKAGE STACKING USING CHIP TO WAFER BONDING | Final Rejection | Intel Corporation |
| 18400772 | INTEGRATED CIRCUIT STRUCTURES HAVING DIELECTRIC ANCHOR AND CONFINED EPITAXIAL SOURCE OR DRAIN STRUCTURE | Final Rejection | Intel Corporation |
| 17847559 | GATE ALL AROUND TRANSISTORS ON ALTERNATE SUBSTRATE ORIENTATION | Final Rejection | Intel Corporation |
| 17711978 | MICROELECTRONIC STRUCTURE INCLUDING DIE BONDING FILM BETWEEN EMBEDDED DIE AND SURFACE OF SUBSTRATE CAVITY, AND METHOD OF MAKING SAME | Final Rejection | Intel Corporation |
| 18495837 | SENSOR ELECTRONIC DEVICE | Final Rejection | Texas Instruments Incorporated |
| 17815457 | CO-PACKAGE FOR QUBITS AND PARAMETRIC JOSEPHSON DEVICES | Non-Final OA | International Business Machines Corporation |
| 18414292 | BARRIER FOR LIQUID METAL THERMAL INTERFACE MATERIAL IN AN ELECTRONIC DEVICE | Non-Final OA | NVIDIA CORPORATION |
| 18317736 | AVALANCHE PHOTODIODE USING A SILICON CAP LAYER | Non-Final OA | Cisco Technology, Inc. |
| 18673204 | SEMICONDUCTOR PACKAGE AND METHOD OF FORMING THE SAME | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18303822 | ISOLATION OF ADJACENT STRUCTURES | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18156847 | SEMICONDUCTOR DIE PACKAGE AND METHODS OF FORMATION | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
| 18783347 | INTEGRATED PHOTORESIST REMOVAL AND LASER ANNEALING | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18581604 | Methods, Structures and Devices for Intra-Connection Structures | Non-Final OA | Taiwan Semiconductor Manufacturing Co., Ltd. |
| 18766911 | SEMICONDUCTOR PACKAGE | Non-Final OA | SAMSUNG ELECTRO-MECHANICS CO., LTD. |
| 18441484 | DIRECT-COOLING FOR SEMICONDUCTOR DEVICE MODULES | Final Rejection | SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy76.5% of resolved applications examined by Andres F Munoz were allowed (728 resolved cases), compared with 85.2% across Art Unit 2818 over the last five years.
This examiner's interview lift is +17.3 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Andres F Munoz took 817 days on average from filing to allowance.
Andres F Munoz examines applications in Art Unit 2818 in Tech Center 2800 (Semiconductors, Circuits & Optics).
