DETAILED ACTION
This correspondence is in response to the communications received 12/30/2025. Claims 1, 5, 6, 8-11, 16, 17, 19, and 20 have been amended. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment to the specification overcomes the objection outlined in the previous Office Action. The objection is withdrawn.
Applicant’s amendments to claims 1 and 11 overcome the objections outlined in the previous Office Action. The objections are withdrawn.
Applicant’s amendments to claims 9, 10, and 16 overcome the 112(b) rejections outlined in the previous Office Action. The rejections are withdrawn.
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
Applicant asserts that Peitz (US 11,088,134 B2) discloses power supply lines in the context of an integrated circuit, and not for diode biasing and that the frontside metal lines of Hung et al. (US 11,569,223 B2, hereinafter ‘223) are not equivalent to the power rails of Peitz.
In response to applicant's argument that Peitz is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, Peitz teaches power supply lines in an integrated circuit, which are pertinent to the ESD protection circuit of '223 which includes power rails.
As discussed in the previous office action, ‘223 states “frontside metal lines FM and/or the backside metal lines BM may serve as the power rails VSS and VDD shown in FIG. 1” (col. 4, lines 38-40). Peitz similarly teaches “The power supply rails belong to a power supply network, and the two left power supply rails 101, 102 supply the integrated circuit with a first supply voltage (e.g. power, VDD, or VCC) and the two right power supply rails 103, 104 supply the integrated circuit with a second supply voltage (e.g. ground or VSS)” (col. 8, lines 24-30). Thus, one having ordinary skill in the art would equate FM and BM of ‘223 which serve as power rails carrying VSS and VDD with 101 and 102 of Peitz which serve as power supply rails also carrying VDD and VSS. Further, as Peitz is relied upon only to rename the existing elements of ‘223, and in view of In re Oetiker, providing electrical connections to the diodes of ‘223 to a power network is sufficient motivation to modify the system of ‘223 with the teachings of Peitz.
Applicant further asserts Chiang et al (US 11,450,665 B2) discloses device orientation and transistor structures and is therefore not relevant to ESD protection architectures and that the combination of Chiang with ‘223 and Peitz requires impermissible hindsight reconstruction.
In response to applicant's argument that Chiang is nonanalogous art, it has been held that a prior art reference must either be in the field of the inventor’s endeavor or, if not, then be reasonably pertinent to the particular problem with which the inventor was concerned, in order to be relied upon as a basis for rejection of the claimed invention. See In re Oetiker, 977 F.2d 1443, 24 USPQ2d 1443 (Fed. Cir. 1992). In this case, and as acknowledged by the Applicant, Chiang teaches semiconductor device orientation, and more specifically, Chiang teaches power rails in relation to device orientation. As the instant application discloses a semiconductor device with power rails, Chiang is therefore pertinent.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Therefore, the rejection of independent claims 1 and 12 is maintained.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, an electrostatic discharge (ESD) protection device ("ESD protection structure and circuit 50"), comprising:
a first diode ("diode 2") comprising a first cathode ("N+ substrate region 6") and first anode ("P+ substrate region 8"), the first cathode connected to a first power rail ("backside power wire 18", as seen in Fig. 1, 6 is connected to 18 via “contact 16”) within a backside power distribution network (BSPDN) ("Backside power wire 18 and backside power wire 19 are a part of the BSPDN of the ESD protection structure of the ESD protection structure and circuit 50", [0057]); and
a second diode ("diode 3") comprising a second cathode ("N+ substrate region 9") and second anode ("P+ substrate region 7 "), the second anode connected to a second power rail ("backside power wire 19", as seen in Fig. 1, 7 is connected to 19 via “contact 17”) within the BSPDN (see above).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 and 12-15 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 11,569,223 B2, hereinafter “’223”) in view of Peitz (US 11,088,134 B2, hereinafter “Peitz”) in view of Chiang et al. (US 11,450,665 B2, hereinafter “Chiang”).
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Regarding claim 1, Figs. 1-25 of ‘223 disclose an electrostatic discharge (ESD) protection device (“semiconductor structure 110A/110B may form the diode D1/D2 in the ESD protection circuit 220 in FIG. 1”, col. 3, lines 35-37), comprising:
a first diode (110B/D2 is a first diode) comprising a first cathode (“second doped epitaxial feature 116”, col. 3, lines 42-43, as seen in Fig. 2, “116B” is an instance of 116 specific to 110B, and it is known in the art that the n-type region of a diode is the cathode, Fig. 2 further shows that 116B is n-type, therefore 116B is a first cathode, this definition of a cathode is further utilized below) and first anode (“first doped epitaxial feature 112”, col. 3, lines 40-41, as seen in Fig. 2, “112B” is an instance of 112 specific to 110B, and it is known in the art that the p-type region of a diode is the anode, Fig. 2 further shows that 112B is p-type, therefore 112B is a first anode, this definition of a anode is further utilized below), the first cathode connected to a first power rail (“frontside metal lines FM and/or the backside metal lines BM may serve as the power rails VSS and VDD shown in FIG. 1”, col. 4, lines 38-40, as seen in Fig. 2, “FMB” is an instance of FM specific to 110B, also seen in Fig. 2, 116B is connected to FMB through “frontside vias VD” and “MDB”, where MDB is an instance of “contact MD” specific to 110B); and
a second diode (110A/D1 is a second diode) comprising a second cathode (“first doped epitaxial feature 112”, col. 3, lines 40-41, as seen in Fig. 2, “112A” is an instance of 112 specific to 110A that is n-type and is therefore a second cathode) and second anode (“second doped epitaxial feature 116”, col. 3, lines 42-43, as seen in Fig. 2, “116A” is an instance of 116 specific to 110A that is p-type and is therefore a second anode), the second anode connected to a second power rail (as seen in Fig. 2, “FMA” is an instance of FM specific to 110A, also seen in Fig. 2, 116A is connected to FMAB through “frontside vias VD” and “MDA”, where MDA is an instance of “contact MD” specific to 110A).
Figs. 1-25 of ‘223 fail to disclose “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN.”
However, in a similar field of endeavor, Fig. 1 of Peitz teaches a first power rail within a backside power distribution network (BSPDN) (“The power supply rails belong to a power supply network, and the two left power supply rails 101, 102 supply the integrated circuit with a first supply voltage (e.g. power, VDD, or VCC) and the two right power supply rails 103, 104 supply the integrated circuit with a second supply voltage (e.g. ground or VSS)”, col. 8, lines 24-30, FMB of ‘223 is equivalent to 101 and 102 of Peitz and is thus a power rail within a power supply network. While FMB is a “frontside metal line”, the frontside/backside definition varies and will be elaborated on by a secondary reference below); and
a second power rail within the BSPDN (MDA of ‘223 is equivalent to 103 and 104 of Peitz and is thus a power rail within a power supply network).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN” as taught by Peitz in the system of ‘223 for the purpose of providing electrical connections so that the diodes can be utilized in the ESD protection function.
‘223 in combination with Peitz fails to disclose “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN”
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However, in a similar field of endeavor, Fig. 37B of Chiang teaches a first power rail within a backside power distribution network (BSPDN) (as seen in Fig. 37B, the bottom of the device is called the frontside, therefore BMA and BMB of ‘223 which are also located in the bottom of 110A and 110B as seen in Fig. 2 of ‘223 could be defined as being on the frontside, and FMA and FMB which are located in the top of 110A and 11B as being on the backside thus making FMB a first power rail within a backside power distribution network); and
a second power rail within the BSPDN (see above discussion, FMA is a second power rail within a backside power distribution network).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN” as taught by Chiang in the system of ‘223 in combination with Peitz for the purpose of providing a robust ESD protection path configuration to prevent destructive current flow during an ESD event.
Regarding claim 2, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the ESD protection device of claim 1, Figs. 1-25 of ‘223 further disclose wherein the BSPDN provides a VDD potential to the first power rail (as seen in Fig. 1, VDD is connected to the cathode of D2, and as seen in Fig. 2 this connection is through FMB) and provides a VSS potential to the second power rail (as seen in Fig. 1, VSS is connected to the anode of D1, and as seen in Fig. 2 this connection is through FMA).
Regarding claim 3, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the ESD protection device of claim 1, Figs. 1-25 of ‘223 further disclose further comprising:
a frontside back end of the line (BEOL) conductive structure (as seen in Fig. 1, the element “CS” is a conductive structure connecting D1, D2, “input/output pad 212”, col. 3, lines 13, and “internal circuit 210”, col. 3, lines 13, ‘223 states “BEOL process includes processes related to fabricating a multilayer interconnect (MLI) feature that interconnects IC features”, col. 3, lines 5-7, therefore CS is a BEOL conductive structure, ‘223 does not specify that the connections represented by CS are frontside elements, a secondary reference is used to position the conductive structure below) electrically connected to the first anode and to the second cathode (as seen in Fig. 1, CS is connected to the anode of D2, and the cathode of D1).
Fig. 37B of Chiang further discloses further comprising:
a frontside back end of the line (BEOL) conductive structure (“method 100 (FIG. 1B) also includes an operation 126 to performs mid-end-of-line (MEOL) processes and back-end-of-line (BEOL) processes at the frontside of the device 200, thereby forming an interconnect structure 360 on the frontside of the device 200. The interconnect structure 360 has various conductive features, such as via features and metal lines in different metal layers”, col. 17, lines 4-10, 360 of Chiang is equivalent to CS of ‘223).
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Regarding claim 4, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the ESD protection device of claim 3, Figs. 1-25 of ‘223 further disclose further comprising a substrate (together “substrate 310”, col. 4, lines 58-59, and “epitaxial stack 320”, col. 4, line 57, form a multilayer substrate), wherein the first diode comprises a first diode stack of doped regions (together “first doped epitaxial feature 112”, col. 3, lines 40-41, “intrinsic epitaxial feature 114”, col. 3, line 41, and “second doped epitaxial feature 116”, col. 3, lines 42-43, form two diode stacks of doped regions, the instance of 112, 114, and 116 corresponding to 110B comprise a first diode stack of doped regions, 112, 114 and 116 of Fig. 2 are equivalent to “first doped epitaxial features 390”, col. 11, line 10, “intrinsic epitaxial feature 400”, col. 12, line 19, and “second doped epitaxial features 410” col. 13, line 7, of Figs. 6A-15 respectively) within the substrate (as seen in Figs. 6B and 19, 390, 400, and 410 are in 320), and wherein the second diode comprises a second diode stack of doped regions (the instance of 112, 114, and 116 corresponding to 110A comprise a second diode stack of doped regions) within the substrate (as previously mentioned, 390, 400, and 410 are in 320).
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Regarding claim 12, Figs. 1-25 of ‘223 disclose a semiconductor integrated circuit (IC) device (“integrated circuit 300”) comprising:
a logic region (“the PFET device and the NFET device in the regions 300B and 300C may form the internal circuit 210 in FIG. 1”, col. 9, lines 2-4, as PFET and NFET devices are transistors, 300B and 300C are therefore a logic region) and an electrostatic discharge (ESD) region (“region 300A may form the ESD protection circuit 220 in FIG. 1”, col. 9, lines 1-2);
the logic region comprising a first source/drain (S/D), a second S/D (“source/drain features (e.g., the features 370/410) in the regions 300B and 300C”, col. 18, lines 59-60, the left instance of 410 in 300C as seen in Fig. 23 is a first S/D, the right instance of 410 in 300C as seen in Fig. 23 is a second S/D), one or more nanolayer channels (“channel regions (e.g., the nanosheets 324)”, col. 18, lines 44-45) connected to the first S/D and connected to the second S/D (as seen in Fig. 6B, 324 is connected to 370 and 410), and a gate structure (“gate structure 430”, col. 15, line 5) around the one or more nanolayer channels (as seen in Fig. 6B. 430 is around 324); and
the ESD region comprising:
a first diode (110B/D2 is a first diode) and a second diode (110A/D1 is a second diode), the first diode comprising a first anode (“second doped epitaxial feature 116”, col. 3, lines 42-43, as seen in Fig. 2, “116B” is an instance of 116 specific to 110B, and it is known in the art that the n-type region of a diode is the cathode, Fig. 2 further shows that 116B is n-type, therefore 116B is a first cathode, this definition of a cathode is further utilized below) and a first cathode (“first doped epitaxial feature 112”, col. 3, lines 40-41, as seen in Fig. 2, “112B” is an instance of 112 specific to 110B, and it is known in the art that the p-type region of a diode is the anode, Fig. 2 further shows that 112B is p-type, therefore 112B is a first anode, this definition of a anode is further utilized below) that is connected to a first power rail (“frontside metal lines FM and/or the backside metal lines BM may serve as the power rails VSS and VDD shown in FIG. 1”, col. 4, lines 38-40, as seen in Fig. 2, “FMB” is an instance of FM specific to 110B, also seen in Fig. 2, 116B is connected to FMB through “frontside vias VD” and “MDB”, where MDB is an instance of “contact MD” specific to 110B), the second diode comprising a second cathode (“first doped epitaxial feature 112”, col. 3, lines 40-41, as seen in Fig. 2, “112A” is an instance of 112 specific to 110A that is n-type and is therefore a second cathode) and second anode (“second doped epitaxial feature 116”, col. 3, lines 42-43, as seen in Fig. 2, “116A” is an instance of 116 specific to 110A that is p-type and is therefore a second anode) that is connected to a second power rail (as seen in Fig. 2, “FMA” is an instance of FM specific to 110A, also seen in Fig. 2, 116A is connected to FMAB through “frontside vias VD” and “MDA”, where MDA is an instance of “contact MD” specific to 110A).
Figs. 1-25 of ‘223 fail to disclose “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN.”
However, in a similar field of endeavor, Fig. 1 of Peitz teaches a first power rail within a backside power distribution network (BSPDN) (“The power supply rails belong to a power supply network, and the two left power supply rails 101, 102 supply the integrated circuit with a first supply voltage (e.g. power, VDD, or VCC) and the two right power supply rails 103, 104 supply the integrated circuit with a second supply voltage (e.g. ground or VSS)”, col. 8, lines 24-30, FMB of ‘223 is equivalent to 101 and 102 of Peitz and is thus a power rail within a power supply network. While FMB is a “frontside metal line”, the frontside/backside definition varies and will be elaborated on by a secondary reference below); and
a second power rail within the BSPDN (MDA of ‘223 is equivalent to 103 and 104 of Peitz and is thus a power rail within a power supply network).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN” as taught by Peitz in the system of ‘223 for the purpose of providing electrical connections so that the diodes can be utilized in the ESD protection function.
‘223 in combination with Peitz fails to disclose “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN”.
However, in a similar field of endeavor, Fig. 37B of Chiang teaches a first power rail within a backside power distribution network (BSPDN) (as seen in Fig. 37B, the bottom of the device is called the frontside, therefore BMA and BMB of ‘223 which are also located in the bottom of 110A and 110B as seen in Fig. 2 of ‘223 could be defined as being on the frontside, and FMA and FMB which are located in the top of 110A and 11B as being on the backside thus making FMB a first power rail within a backside power distribution network); and
a second power rail within the BSPDN (see above discussion, FMA is a second power rail within a backside power distribution network).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first power rail within a backside power distribution network (BSPDN); and
a second power rail within the BSPDN” as taught by Chiang in the system of ‘223 in combination with Peitz for the purpose of providing a robust ESD protection path configuration to prevent destructive current flow during an ESD event.
Regarding claim 13, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the semiconductor IC device of claim 12, Figs. 1-25 of ‘223 further disclose wherein the BSPDN provides a VDD potential to the first power rail (as seen in Fig. 1, VDD is connected to the cathode of D2, and as seen in Fig. 2 this connection is through FMB) and provides a VSS potential to the second power rail (as seen in Fig. 1, VSS is connected to the anode of D1, and as seen in Fig. 2 this connection is through FMA).
Regarding claim 14, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the semiconductor IC device of claim 12, Figs. 1-25 of ‘223 further disclose further comprising:
a frontside back end of the line (BEOL) conductive structure (“front-side multilayer interconnection (MLI) structure 460”, “BEOL process includes processes related to fabricating a multilayer interconnect (MLI) feature that interconnects IC features”, col. 3, lines 5-7, therefore 460 is a frontside BEOL conductive structure) electrically connected to the first anode, to the second cathode, and to the second S/D (“460 may have include a plurality of front-side metallization layers 462”, col. 16, lines 38-39, “the front-side conductive vias CV in the bottommost front-side metallization layer 462 are respectively in contact with the contact 450 to make electrical connection to the epitaxial features 390 and 410”, col. 16, lines 54-57, as 112, 114 and 116 of Fig. 2 are equivalent to “first doped epitaxial features 390”, “intrinsic epitaxial feature 400”, and “second doped epitaxial features 410” of Figs. 6A-15 respectively, 460 is therefore electrically connected to 410/116B, 410/116A, and the second S/D 410).
Regarding claim 15, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the semiconductor IC device of claim 14, Figs. 1-25 of ‘223 further disclose wherein the ESD region further comprises a substrate (together “substrate 310”, col. 4, lines 58-59, and “epitaxial stack 320”, col. 4, line 57, form a multilayer substrate), wherein the first diode comprises a first diode stack of doped regions (together “first doped epitaxial feature 112”, col. 3, lines 40-41, “intrinsic epitaxial feature 114”, col. 3, line 41, and “second doped epitaxial feature 116”, col. 3, lines 42-43, form two diode stacks of doped regions, the instance of 112, 114, and 116 corresponding to 110B comprise a first diode stack of doped regions, 112, 114 and 116 of Fig. 2 are equivalent to “first doped epitaxial features 390”, col. 11, line 10, “intrinsic epitaxial feature 400”, col. 12, line 19, and “second doped epitaxial features 410” col. 13, line 7, of Figs. 6A-15 respectively) within the substrate (as seen in Figs. 6B and 19, 390, 400, and 410 are in 320), and wherein the second diode comprises a second diode stack of doped regions (the instance of 112, 114, and 116 corresponding to 110A comprise a second diode stack of doped regions) within the substrate (as previously mentioned, 390, 400, and 410 are in 320).
Claims 5-11 and 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hung et al. (US 11,569,223 B2, hereinafter “’223”) in view of Peitz (US 11,088,134 B2, hereinafter “Peitz”) in view of Chiang et al. (US 11,450,665 B2, hereinafter “Chiang”) in view of Hung et al. (US 11,973,075 B2, hereinafter “’075”) in view of Shen et al. (US 10,930,637 B2, hereinafter “Shen”) in view of Chu et al. (US 12,148,807 B2, hereinafter “Chu”) in view of Takeuchi et al. (US 10,840,335 B2, hereinafter “Takeuchi”).
Regarding claim 5, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the ESD protection device of claim 4, Figs. 1-25 of ‘223 further disclose wherein the first diode stack comprises a lightly doped n-type well (‘223 discloses “the intrinsic epitaxial feature 114 may be doped with a p-type or an n-type, and with a doping concentration lower than that of the first and second doped epitaxial features 112 and 116”, col. 4, lines 20-23, but does not specify which instance of 114 is p-type or n-type, nor that 114 is a well, instead a secondary reference will be used below).
‘223 in combination with Peitz and Chaing fails to disclose “wherein the first diode stack comprises a lightly doped n-type well and wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate.”
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However, in a similar field of endeavor, Fig. 1 of ‘075 teaches wherein the first diode stack comprises a doped n-type well (“N-well 131A”, col. 4, line 63, 131A of ‘075 shows a possible alternative configuration of 114B of ‘223, while ‘075 teaches a doped n-type well, it does not teach a lightly doped n-type well, instead a secondary reference will be used below).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first diode stack comprises a doped n-type well” as taught by ‘075 in the system of ‘223 in combination with Peitz and Chiang for the purpose of defining the dopant type of the well adjacent to the heavily doped regions.
‘223 in combination with Peitz, Chiang and ‘075 fails to disclose “wherein the first diode stack comprises a lightly doped n-type well and wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate”
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 5 and 6 of Shen teach wherein the first diode stack comprises a lightly doped n-type well (“the second doped layer 22 can be alternatively an N type lightly doped well instead of a N type epitaxial layer”, col. 5, lines 2-4, thus indicating that 114B of ‘223 which is n-type as per ‘075 could alternatively be a lightly doped well).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first diode stack comprises a lightly doped n-type well” as taught by Shen in the system of ‘223 in combination with Peitz, Chiang, and ‘075 for the purpose of eliminating the deposition and etching steps necessary to form a doped epitaxy layer as instead “the N type lightly doped well and/or the P type lightly doped well can be formed through an ion implantation technology” (col. 5, lines 9-11).
‘223 in combination with Peitz, Chiang, ‘075, and Shen fails to disclose “wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate”.
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 1C of Chu teaches a highly doped p-type epitaxially grown region (“epitaxial contact structure 146 can be epitaxially grown on p-type S/D regions using precursors including a silicon precursor, a germanium precursor, and a doping precursor”, col. 12, lines 66-67 and col. 13, lines 1 and 2, where “The doping precursor can include diborane (B2H6) or other p-type doping precursor”, col. 13, lines 5-6, and “epitaxial contact structure 146 can include an active dopant higher than about 1×1021 cm-3 to reduce its resistance”, col. 13, lines 13-15, as per paragraph [0071] of the specification, 1×1021 cm-3 is considered a typical concentration of a highly doped region) is vertically above the first diode stack (“S/D region 110B”, 110B of Chu is equivalent to 112B of ‘223, and after the reorientation of 110A and 110B as per Chiang, 146 of Chu is vertically above 110B of ‘223).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a highly doped p-type epitaxially grown region is vertically above the first diode stack” as taught by Chu in the system of ‘223 in combination with Peitz, Chiang, ‘075, and Shen to reduce contact resistance.
‘223 in combination with Peitz, Chiang, ‘075, Shen, and Chu fails to disclose “wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate”.
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However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 6 of Takeuchi teaches a highly doped p-type epitaxially grown region (“upper source region 205”, col. 12, line 24, while 205 is n-type, Takeuchi states “the upper source/drain regions 105, 107 and the lower source/drain regions 104, 106 are N-type for a N-channel device, but these regions may also be P-type for an P-channel device as well (this applies to other configurations described herein as well)”, col. 12, lines 1-6, furthermore, Takeuchi is only used to teach the geometrical relationship of the device, one having ordinary skill in the art would recognize the need to change dopant type to match the preceding device layer as per Chu) is vertically above the first diode stack (“lower source region 204”, col. 12, line 23, 204 of Takeuchi is equivalent to 112B of ‘223) upon a top surface of the substrate (“substrate 201”, col. 12, lines 18-19, of Takeuchi is equivalent to 310 and 320 of ‘223, and as seen in Fig. 6, 205 is upon a top surface of 210).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate” as taught by Takeuchi in the system of ‘223 in combination with Peitz, Chiang, ‘075, Shen, and Chu for the purpose of reducing the contact resistance without modifying the underlying structure, i.e. by using an additional element on top of the device structure.
Regarding claim 6, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the ESD protection device of claim 5, Figs. 1-25 of ‘223 further disclose wherein the first diode stack comprises a lightly doped p-type well (‘223 discloses “the intrinsic epitaxial feature 114 may be doped with a p-type or an n-type, and with a doping concentration lower than that of the first and second doped epitaxial features 112 and 116”, col. 4, lines 20-23, but does not specify which instance of 114 is p-type or n-type, nor that 114 is a well, instead a secondary reference will be used below).
As previously presented in the combination rejection of claim 5, Fig. 1 of ‘075 further discloses wherein the second diode stack comprises a lightly doped p-type well (“P-well 163A”, 163A of ‘075 shows a possible alternative configuration of 114A of ‘223, while ‘075 teaches a doped p-type well, it does not teach a lightly doped p-type well, instead a secondary reference will be used below).
As previously presented in the combination rejection of claim 5, Figs. 5 and 6 of Shen further disclose wherein the first diode stack comprises a lightly doped p-type well (“the second doped layer 22 can be alternatively a P type lightly doped well instead of a P type epitaxial layer”, col. 5, lines 6-8, thus indicating that 114A of ‘223 which is p-type as per ‘075 could alternatively be a lightly doped well).
As previously presented in the combination rejection of claim 5, Fig. 1C of Chu further discloses a highly doped p-type epitaxially grown region (“epitaxial contact structure 146 can be epitaxially grown on n-type S/D regions using precursors including a silicon precursor and a doping precursor”, col. 13, lines 16-18, where “The doping precursor can include phosphine (PH3), arsine (AsH3), or other [n]-type doping precursor”, col. 13, lines 20-21, and “epitaxial contact structure 146 can include an active dopant higher than about 1×1021 cm-3 to reduce its resistance”, col. 13, lines 27-29, as per paragraph [0071] of the specification, 1×1021 cm-3 is considered a typical concentration of a highly doped region) is vertically above the first diode stack (“S/D region 110B”, 110B of Chu is equivalent to 112A of ‘223, and after the reorientation of 110A and 110B as per Chiang, 146 of Chu is vertically above 110A of ‘223).
As previously presented in the combination rejection of claim 5, Fig. 6 of Takeuchi further discloses a highly doped n-type epitaxially grown region (“upper source region 205”, as seen in Fig. 6, 205 is highly doped n-type) is vertically above the second diode stack (“lower source region 204”, 204 of Takeuchi is equivalent to 112A of ‘223) upon the top surface of the substrate (as seen in Fig. 6, 205 is upon a top surface of 210).
Regarding claim 7, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the ESD protection device of claim 6, Fig. 1C of Chu further discloses further comprising a first frontside contact (“metal contact 150”, col. 7, lines 11-12, 150 of Chu is equivalent to “VBB” of ‘223 where VBB is an instance of “backside contact via VB” specific to 110B shown in Fig. 2 of ‘223, and after the reorientation of 110A and 11B of ‘223 as per Chiang, VB is a frontside contact) upon the highly doped p-type epitaxially grown region (as seen in Fig. 1C, 150 is upon 146); and
a second frontside contact (as Chu is only being used to modify the structure of ‘223, 150 of Chu is also equivalent to “VBA” of ‘223 where VBA is an instance of “backside contact via VB” specific to 110B shown in Fig. 2 of ‘223, and after the reorientation of 110A and 11B of ‘223 as per Chiang, VB is a frontside contact) upon the highly doped n-type epitaxially grown region (as seen in Fig. 1C, 150 is upon 146).
Regarding claim 8, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the ESD protection device of claim 7, Figs. 1-25 of ‘223 further disclose wherein the frontside BEOL conductive structure is connected to the first frontside contact and to the second frontside contact (as seen in Fig. 1, CS is connected to the anode of D2 and the cathode of D1, and ‘223 states “The frontside metal lines FM and the backside metal lines BM may be designed by suitable routing designs for realizing the circuit shown in FIG. 1”, col. 4, lines 35-37, as BM connects to 112A and 112B, via VBA and VBB respectively, CS which is realized by BM is connected to VBA and VBB).
Regarding claim 9, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the ESD protection device of claim 6, Figs. 1-25 of ‘223 further disclose wherein the first diode stack further comprises a highly doped n-type region (as seen in Fig. 2, 116B is a highly doped n-type region) below the lightly doped n-type well (‘223 discloses “the intrinsic epitaxial feature 114 may be doped with a p-type or an n-type, and with a doping concentration lower than that of the first and second doped epitaxial features 112 and 116”, col. 4, lines 20-23, but does not specify which instance of 114 is p-type or n-type, nor that 114 is a well, instead a secondary reference will be used below, further, Fig. 2 shows “114B”, the instance of 114 specific to 110B, as being below 116B, as taught by Chiang, the device orientation is relative, and as per the orientation defined by Chiang, 116B is below 114B as it is closer to the device backside) within the substrate (as discussed above, 112, 114 and 116 of Fig. 2 are equivalent to 390, 400, and 410 of Figs. 6A-15 respectively and as seen in Figs. 6B and 19, 390, 400, and 410 are in 320) and wherein the second diode stack further comprises a highly doped p-type region (as seen in Fig. 2, 116A is a highly doped p-type region) below the lightly doped p-type well (as above, the instance of 114 specific to 110A, “114A” is lightly doped region, but not specifically a well, however using the orientation defined by Chiang, 116A is below 114A) within the substrate (390, 400, and 410 are in 320).
Fig. 1 of ‘075 further discloses a highly doped n-type region (“heavily N-doped regions 135A”, col. 4, lines 50-51, 135A of ‘075 is equivalent to 116B of ‘223) below the lightly doped n-type well (“N-well 131A”, col. 4, line 62, 131A of ‘075 shows a possible alternative configuration of 114B of ‘223, while ‘075 teaches a doped n-type well, it does not teach a lightly doped n-type well, instead a secondary reference will be used below) and a highly doped p-type region (“heavily P-doped regions 161A”, col. 3, lines 61-62, 161 of ‘075 is equivalent to 116A of ‘223) below the lightly doped p-type well (“P-well 163A”, col. 4, line 18, 163A of ‘075 shows a possible alternative configuration of 114A of ‘223, while ‘075 teaches a doped p-type well, it does not teach a lightly doped p-type well, instead a secondary reference will be used below).
Figs. 5 and 6 of Shen further disclose a highly doped n-type region below the lightly doped n-type well (“the second doped layer 22 can be alternatively an N type lightly doped well instead of a N type epitaxial layer”, col. 5, lines 2-4, thus indicating that 114B of ‘223 which is n-type as per ‘075 could alternatively be a lightly doped well) and a highly doped p-type region below the lightly doped p-type well (“the second doped layer 22 can be alternatively a P type lightly doped well instead of a P type epitaxial layer”, col. 5, lines 6-8, thus indicating that 114A of ‘223 which is p-type as per ‘075 could alternatively be a lightly doped well).
Regarding claim 10, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the ESD protection device of claim 9, Figs. 1-25 of ‘223 further disclose further comprising:
a first backside contact (MDB is a first backside contact after applying the orientation of Chiang) upon the highly doped n-type region (as seen in Fig. 2, 116B is a highly doped n-type region, and MDB is upon 116B), wherein the highly doped n-type region is the first cathode (as discussed previously, 116B is the first cathode); and
a second backside contact (MDA is a first backside contact after applying the orientation of Chiang) upon the highly doped p-type region (as seen in Fig. 2, 116A is a highly doped p-type region, and MDA is upon 116A), wherein the highly doped p-type region is the second anode (as discussed previously, 116A is the first cathode).
Regarding claim 11, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the ESD protection device of claim 10, Figs. 1-25 of ‘223 further disclose wherein the first backside contact is connected to the first power rail (as seen in Fig. 2, MDB is connected to FMB), and wherein the second backside contact is connected to the second power rail (as seen in Fig. 2, MDA is connected to FMA).
Regarding claim 16, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang disclose the semiconductor IC device of claim 15, Figs. 1-25 of ‘223 further disclose wherein the first diode stack comprises a lightly doped n-type well (‘223 discloses “the intrinsic epitaxial feature 114 may be doped with a p-type or an n-type, and with a doping concentration lower than that of the first and second doped epitaxial features 112 and 116”, col. 4, lines 20-23, but does not specify which instance of 114 is p-type or n-type, nor that 114 is a well, instead a secondary reference will be used below), and the substrate (together 310 and 320 form a multilayer substrate).
‘223 in combination with Peitz and Chaing fails to disclose “wherein the first diode stack comprises a lightly doped n-type well and wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate.”
However, in a similar field of endeavor, Fig. 1 of ‘075 teaches wherein the first diode stack comprises a doped n-type well (“N-well 131A”, col. 4, line 62, 131A of ‘075 shows a possible alternative configuration of 114B of ‘223, while ‘075 teaches a doped n-type well, it does not teach a lightly doped n-type well, instead a secondary reference will be used below).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first diode stack comprises a doped n-type well” as taught by ‘075 in the system of ‘223 in combination with Peitz and Chiang for the purpose of doping the well so that the conductivity levels can support the basic function of the device.
‘223 in combination with Peitz, Chiang and ‘075 fails to disclose “wherein the first diode stack comprises a lightly doped n-type well and wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate”
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Figs. 5 and 6 of Shen teach wherein the first diode stack comprises a lightly doped n-type well (“the second doped layer 22 can be alternatively an N type lightly doped well instead of a N type epitaxial layer”, col. 5, lines 2-4, thus indicating that 114B of ‘223 which is n-type as per ‘075 could alternatively be a lightly doped well).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the first diode stack comprises a lightly doped n-type well” as taught by Shen in the system of ‘223 in combination with Peitz, Chiang, and ‘075 for the purpose of eliminating the deposition and etching steps necessary to form a doped epitaxy layer as instead “the N type lightly doped well and/or the P type lightly doped well can be formed through an ion implantation technology” (col. 5, lines 9-11).
‘223 in combination with Peitz, Chiang, ‘075, and Shen fails to disclose “wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 1C of Chu teaches a highly doped p-type epitaxially grown region (“epitaxial contact structure 146 can be epitaxially grown on p-type S/D regions using precursors including a silicon precursor, a germanium precursor, and a doping precursor”, col. 12, lines 66-67 and col. 13, lines 1 and 2, where “The doping precursor can include diborane (B2H6) or other p-type doping precursor”, col. 13, lines 5-6, and “epitaxial contact structure 146 can include an active dopant higher than about 1×1021 cm-3 to reduce its resistance”, col. 13, lines 13-15, as per paragraph [0071] of the specification, 1×1021 cm-3 is considered a typical concentration of a highly doped region) is vertically above the first diode stack (“S/D region 110B”, 110B of Chu is equivalent to 112B of ‘223, and after the reorientation of 110A and 110B as per Chiang, 146 of Chu is vertically above 110B of ‘223).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a highly doped p-type epitaxially grown region is vertically above the first diode stack” as taught by Chu in the system of ‘223 in combination with Peitz, Chiang, ‘075, and Shen to reduce contact resistance.
‘223 in combination with Peitz, Chiang, ‘075, Shen, and Chu fails to disclose “wherein a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate”.
However, in a device that is reasonably pertinent to the particular problem with which the inventor was concerned, Fig. 6 of Takeuchi teaches a highly doped p-type epitaxially grown region (“upper source region 205”, col. 12, line 24, while 205 is n-type, Takeuchi states “the upper source/drain regions 105, 107 and the lower source/drain regions 104, 106 are N-type for a N-channel device, but these regions may also be P-type for an P-channel device as well (this applies to other configurations described herein as well)”, col. 12, lines 1-6, furthermore, Takeuchi is only used to teach the geometrical relationship of the device, one having ordinary skill in the art would recognize the need to change dopant type to match the preceding device layer as per Chu) is vertically above the first diode stack (“lower source region 204”, col. 12, line 23, 204 of Takeuchi is equivalent to 112B of ‘223) upon a top surface of the substrate (“substrate 201”, col. 12, lines 18-19, of Takeuchi is equivalent to 310 and 320 of ‘223, and as seen in Fig. 6, 205 is upon a top surface of 210).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a highly doped p-type epitaxially grown region is vertically above the first diode stack upon a top surface of the substrate” as taught by Takeuchi in the system of ‘223 in combination with Peitz, Chiang, ‘075, Shen, and Chu for the purpose of reducing the contact resistance without modifying the underlying structure, i.e. by using an additional element on top of the device structure.
Regarding claim 17, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the semiconductor IC device of claim 16, Figs. 1-25 of ‘223 further disclose wherein the first diode stack comprises a lightly doped p-type well (‘223 discloses “the intrinsic epitaxial feature 114 may be doped with a p-type or an n-type, and with a doping concentration lower than that of the first and second doped epitaxial features 112 and 116”, col. 4, lines 20-23, but does not specify which instance of 114 is p-type or n-type, nor that 114 is a well, instead a secondary reference will be used below).
As previously presented in the combination rejection of claim 16, Fig. 1 of ‘075 further discloses wherein the second diode stack comprises a lightly doped p-type well (“P-well 163A”, 163A of ‘075 shows a possible alternative configuration of 114A of ‘223, while ‘075 teaches a doped p-type well, it does not teach a lightly doped p-type well, instead a secondary reference will be used below).
As previously presented in the combination rejection of claim 16, Figs. 5 and 6 of Shen further disclose wherein the first diode stack comprises a lightly doped p-type well (“the second doped layer 22 can be alternatively a P type lightly doped well instead of a P type epitaxial layer”, col. 5, lines 6-8, thus indicating that 114A of ‘223 which is p-type as per ‘075 could alternatively be a lightly doped well).
As previously presented in the combination rejection of claim 16, Fig. 1C of Chu further discloses a highly doped p-type epitaxially grown region (“epitaxial contact structure 146 can be epitaxially grown on n-type S/D regions using precursors including a silicon precursor and a doping precursor”, col. 13, lines 16-18, where “The doping precursor can include phosphine (PH3), arsine (AsH3), or other [n]-type doping precursor”, col. 13, lines 20-21, and “epitaxial contact structure 146 can include an active dopant higher than about 1×1021 cm-3 to reduce its resistance”, col. 13, lines 27-29, as per paragraph [0071] of the specification, 1×1021 cm-3 is considered a typical concentration of a highly doped region) is vertically above the first diode stack (“S/D region 110B”, 110B of Chu is equivalent to 112A of ‘223, and after the reorientation of 110A and 110B as per Chiang, 146 of Chu is vertically above 110A of ‘223).
As previously presented in the combination rejection of claim 16, Fig. 6 of Takeuchi further discloses a highly doped n-type epitaxially grown region (“upper source region 205”, as seen in Fig. 6, 205 is highly doped n-type) is vertically above the second diode stack (“lower source region 204”, 204 of Takeuchi is equivalent to 112A of ‘223) upon the top surface of the substrate (as seen in Fig. 6, 205 is upon a top surface of 210).
Regarding claim 18, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the semiconductor IC device of claim 17, Fig. 1C of Chu further discloses wherein the ESD region further comprises a first frontside contact (“metal contact 150”, col. 7, lines 11-12, 150 of Chu is equivalent to “VBB” of ‘223 where VBB is an instance of “backside contact via VB” specific to 110B shown in Fig. 2 of ‘223, and after the reorientation of 110A and 11B of ‘223 as per Chiang, VB is a frontside contact) upon the highly doped p-type epitaxially grown region (as seen in Fig. 1C, 150 is upon 146) and a second frontside contact (as Chu is only being used to modify the structure of ‘223, 150 of Chu is also equivalent to “VBA” of ‘223 where VBA is an instance of “backside contact via VB” specific to 110B shown in Fig. 2 of ‘223, and after the reorientation of 110A and 11B of ‘223 as per Chiang, VB is a frontside contact) upon the highly doped n-type epitaxially grown region (as seen in Fig. 1C, 150 is upon 146).
As previously presented in the combination rejection of claim 12, Figs. 1-25 of ‘223 further disclose wherein the logic region further comprises a third frontside contact (“contacts 450”, col. 16, line 14, specifically 450 in 300C, as seen in Fig. 23, 450 are on the topside of the device and are therefore frontside contacts) between the second S/D and the frontside BEOL conductive structure (as seen in Fig. 23, 450 are between 410 and 460).
Regarding claim 19, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the semiconductor IC device of claim 17, Figs. 1-25 of ‘223 further disclose wherein the first diode stack further comprises a highly doped n-type region (as seen in Fig. 2, 116B is a highly doped n-type region) below the lightly doped n-type well (as previously mentioned, 114B is a lightly doped n-type well after the modification taught by ‘075 and Chen, further, in the orientation defined by Chiang, 116B is below 114B) within the substrate (as discussed above, 112, 114 and 116 of Fig. 2 are equivalent to 390, 400, and 410 of Figs. 6A-15 respectively and as seen in Figs. 6B and 19, 390, 400, and 410 are in 320) and wherein the second diode stack further comprises a highly doped p-type region (as seen in Fig. 2, 116A is a highly doped p-type region) below the lightly doped p-type well (as previously mentioned, 114A is a lightly doped p-type well after the modification taught by ‘075 and Chen, further, in the orientation defined by Chiang, 116A is below 114A) within the substrate (390, 400, and 410 are in 320).
Regarding claim 20, Figs. 1-25 of ‘223 in combination with Fig. 1 of Peitz and Fig. 37B of Chiang, Fig. 1 of ‘075, Figs. 5 and 6 of Shen, Fig. 1C of Shen, and Fig. 6 of Takeuchi disclose the semiconductor IC device of claim 19, Figs. 1-25 of ‘223 further disclose wherein the ESD region further comprises a first backside contact (MDB is a first backside contact after applying the orientation of Chiang) upon the highly doped n-type region (as seen in Fig. 2, MDB is upon 116B) and a second backside contact (MDA is a first backside contact after applying the orientation of Chiang) upon the highly doped p-type region (as seen in Fig. 2, MDA is upon 116A); and
wherein the logic region further comprises a third backside contact (“backside contact vias 380”) upon the first S/D region (as seen in Fig. 23, depending on orientation, 380 is upon the left instance of 410).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893