DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 9/8/2026 has been entered.
Response to Amendment
Applicant’s amendment filed on 9/8/2026 is acknowledged. Claims 1, 11-12, 18, 21 have been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-21, 26-30 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “wherein the liner further comprises respective sidewalls and a bottom surface in contact with the first gate dielectric” in line 5-7. The first gate dielectric in the claim is identified as 204, and the liner is identified as element 216-L in Fig. 12 of the specification of the instant application. As shown in Fig. 12, only the sidewall or the bottom surface of the liner can be in contact with the first gate dielectric layer 204. So the specification does not have support for the both sidewalls and bottom surface in contact with the first gate dielectric as required in the claim.
Claim 11 recites “a liner comprising a first metal and having respective sidewalls and a bottom surface in contact with the first gate dielectric” in lines 5-7. Claims 18 and 21 recites “wherein the liner further comprises respective sidewalls and a bottom surface in contact with the first gate dielectric” in lines 5-7 of the respective claim. Claim 26 recites “a metal liner comprising a first metal and having respective sidewalls and a bottom surface in contact with the first gate dielectric” in lines 5-7. These all lack support in the specification.
Allowable Subject Matter
Claims 1-21, 26-29 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), 1st paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 1, the prior art of record does not disclose or fairly suggest a field effect transistor device comprising “a metal-insulator-metal (MIM) structure comprising: a liner comprising a first metal, wherein the liner further comprises respective sidewalls and a bottom surface in contact with the first gate dielectric; an insulator in contact with the respective sidewalls and the bottom surface; a second metal in contact with the insulator” and “a floating gate comprising the liner and a sensing surface, wherein the sensing surface is disposed to one side of the MIM structure” along with other limitations of the claim.
Regarding claim 11, the prior art of record does not disclose or fairly suggest a field effect transistor device comprising “a metal-insulator-metal (MIM) structure comprising: a liner comprising a first metal and having respective sidewalls and a bottom surface in contact with the first gate dielectric; an insulator in contact with the respective sidewalls and the bottom surface; and a second metal in contact with the insulator; a floating gate comprising the liner and a sensing surface, wherein the sensing surface is disposed to one side of the MIM structure” along with other limitations of the claim.
Regarding claim 18, the prior art of record does not disclose or fairly suggest a field effect transistor device comprising “a metal-insulator-metal (MIM) structure comprising: a liner comprising a first metal, wherein the liner comprises respective sidewalls and a bottom surface in contact with the first gate dielectric; an insulator in contact with the respective sidewalls and the bottom surface; and a second metal in contact with the insulator; and a floating gate comprising the liner and a sensing surface, wherein the sensing surface is disposed to one side of the MIM structure” along with other limitations of the claim.
Regarding claim 21, the prior art of record does not disclose or fairly suggest a field effect transistor device comprising “a metal-insulator-metal (MIM) structure comprising: a liner comprising a first metal, wherein the liner further comprises respective sidewalls and a bottom surface in contact with the first gate dielectric; an insulator in contact with the respective sidewalls and the bottom surface; and a second metal in contact with the insulator; a floating gate comprising the liner and a sensing surface, wherein the sensing surface is disposed to one side of the MIM structure” along with other limitations of the claim.
Regarding claim 26, the prior art of record does not disclose or fairly suggests “a gate structure comprising: a metal liner comprising a first metal and having respective sidewalls and a bottom surface in contact with the first gate dielectric; an insulator in contact with the respective sidewalls and the bottom surface; and a second metal in contact with the insulator; and a floating gate comprising a sensing surface disposed to one side of the gate structure” along with other limitations of the claim.
The prior art of record are Levon et al. (US 2005/0230271 A1), Choi et al. (KR 101320687 B1), and Cheng et al. (US 2016/0178568 A1).
Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising: a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340); a first gate dielectric (oxide 340) in contact with the semiconductor channel; a metal-insulator-metal (MIM) structure (342-346) comprising: a liner (portion of floating gate 342 starting from the left end to the beginning point of the sensing material 348), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3); an insulator (oxide 344) in contact with the liner; and a second electrode (control gate 346) in contact with the insulator; and a floating gate (the whole floating gate 342) comprising the liner (as defined above, the liner is a left part of the floating gate 342) and a sensing surface (upper surfaces of the sensing material layer 348, which includes a horizontal top surface and two vertical side surfaces), wherein the liner extends to the sensing surface (as defined above), and wherein the sensing surface is configured to sense a sample in contact with the sensing surface (the phrase “is configured to sense a sample” is a functional language, which only requires that the element is capable of performing the function, but not performing the exact function. As the label suggests, this surface is intended for sensing a sample).
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
However, none of the reference above teach an MIM structure satisfying all the limitations as recited above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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