DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of invention I, claims 1-21, in the reply filed on 9/5/2025 is acknowledged. Claims 22-25 have been canceled. Claims 26-29 have been added.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-21 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites “a liner comprising a first metal” in line 5 and “a floating gate comprising the first metal and an extension” in line 9. It is unclear if the liner is the same or different than the floating gate. Figure 13 of the specification shows two elements 216-L and 216-X. The element 216-X is identified as the “extension” in line 9. So the element 216-L must be the first metal. In this case, the floating gate is the combination of 216-L and 216-X (as defined in line 9). However, this introduces an indefinite issue with the “liner”. If the “liner” is just the element 216-L, than one single element 216-L is assigned two different labels, “liner” and “first metal”. If the “liner” can include other elements, then the disclosure of Fig. 13 forces the “liner” to be “floating gate” which is again assigning two different labels to a single element. For the purpose of examination, the Examiner interprets that the “liner” is just the first metal.
Claims 11 and 18 recite the same limitation and suffer the same indefinite issue. The same interpretation is applied to these claims and their dependent claims.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Levon et al. (US 2005/0230271 A1) in view of Choi et al. (KR 101320687 B1).
Regarding claim 1, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 overlapped with oxide layer 340), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the first metal; and
a second electrode (control gate 346) in contact with the insulator; and
a floating gate (342) comprising the liner and an extension (portion of floating gate 342 outside of oxide 344), wherein the extension is disposed to one side of the MIM structure (as shown in Fig. 3), wherein the extension comprises a sensing surface (top surface of floating gate 342 that is coated by sensing material 348) for sensing a sample in contact with the sensing surface (the phrase “for sensing a sample…” is intended use of the sensing surface. As the label suggests, this surface is intended for sensing a sample).
But Levon does not teach that the liner comprising a first metal; and the second electrode is a second metal.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
Regarding claim 2, Levon in view of Choi teaches all limitations of the FET device of claim 1, and further comprising an additional layer (348 in Fig. 3 of Levon) covering the sensing surface.
Regarding claim 3, Levon in view of Choi teaches all limitations of the FET device of claim 2, and also teaches wherein the additional layer comprises a conductive material (as described in [0030] of Levon).
Regarding claim 2, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach the FET device further comprising an additional layer covering the sensing surface.
In a different embodiment (Fig. 6 of Levon), Levon teaches an extension (625-640 in Fig. 6 of Levon) of the floating gate (615) that the sensing surface (top surface of 640) is covered by an additional layer (645), wherein the additional layer comprises an insulating material (glass as stated in [0049] of Levon).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed an additional layer as according to embodiment in Fig. 6 of Levon in order to have protect the sensing surface of Levon.
Regarding claim 4, Levon in view of Choi teaches all limitations of the FET device of claim 2, and also teaches wherein the additional layer comprises an insulating material (as stated in [0049] of Levon).
Regarding claim 7, Levon in view of Choi teaches all limitations of the FET device of claim 1, and also teaches wherein the FET comprises a planar device (as shown in Fig. 3 of Levon).
Regarding claim 10, Levon in view of Choi teaches all limitations of the FET device of claim 1, and also teaches wherein the semiconductor channel comprises a silicon channel (see [0030] of Levon).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, as applied in claim 1, and further in view of Cheng et al. (US 2016/0178568 A1).
Regarding claim 5, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach that the FET device further comprising a well having the sensing surface at a bottom and sides of the well, and wherein the well is configured to contain the sample.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of the well, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
Claims 6, 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, and further in view of Kahya (US 2010/0055699 A1).
Regarding claim 6, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach wherein the FET comprises a nanosheet device.
Kahya teaches a biosensor using a FET (Fig. 1-9 of Kahya). The semiconductor channel of the transistor is a nanosheet structure ([0002] of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 8, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach wherein the FET comprises a FinFET device.
Kahya teaches a biosensor using a finFET on an SOI substrate (Fig. 1-9 and [0003] of Kahya). The semiconductor channel of the transistor is a fin shape structure on an SOI substrate (see Fig. 3a of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 9, Levon in view of Choi teaches all limitations of the FET device of claim 1, and also teaches wherein the FET device comprises a silicon on insulator device ([0003] of Kahya).
Claims 11, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi.
Regarding claim 11, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 overlapped with oxide layer 340), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the first metal; and
a second gate electrode (control gate 346) in contact with the insulator;
a floating gate (342) comprising the liner and an extension (portion of floating gate 342 outside of oxide 344), wherein the extension is disposed to one side of the MIM structure (as shown in Fig. 3), wherein the extension comprises a sensing surface (top surface of floating gate 342 that is coated by sensing material 348) for sensing a sample in contact with the sensing surface (the phrase “for sensing a sample…” is intended use of the sensing surface. As the label suggests, this surface is intended for sensing a sample).
But Levon does not teach that the liner comprising a first metal; and the second gate electrode is a second metal; and the FET device comprising: an additional layer covering the sensing surface, wherein the additional layer comprises a material selected from a group consisting of a conductive material and an insulating material.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach wherein the additional layer comprises a material selected from a group consisting of a conductive material and an insulating material.
In a different embodiment (Fig. 6 of Levon), Levon teaches an extension (625-640 in Fig. 6 of Levon) of the floating gate (615) that the sensing surface (top surface of 640) is covered by an additional layer (645), wherein the additional layer comprises an insulating material (glass as stated in [0049] of Levon).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed an additional layer as according to embodiment in Fig. 6 of Levon in order to have protect the sensing surface of Levon.
Regarding claim 14, Levon in view of Choi teaches all limitations of the FET device of claim 11, and also teaches wherein the FET comprises a planar device (as shown in Fig. 3 of Levon).
Regarding claim 17, Levon in view of Choi teaches all limitations of the FET device of claim 11, and also teaches wherein the semiconductor channel comprises a silicon channel (see [0030] of Levon).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, and further in view of Cheng et al. (US 2016/0178568 A1).
Regarding claim 12, Levon in view of Choi teaches all limitations of the FET device of claim 11, but does not teach wherein the floating gate comprises a well having the sensing surface at a bottom and sides of the well, wherein the well is configured to contain the sample.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of the well, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
Claims 13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, and further in view of Kahya.
Regarding claim 13, Levon in view of Choi teaches all limitations of the FET device of claim 11, but does not teach wherein the FET comprises a nanosheet device.
Kahya teaches a biosensor using a FET (Fig. 1-9 of Kahya). The semiconductor channel of the transistor is a nanosheet structure ([0002] of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 15, Levon in view of Choi teaches all limitations of the FET device of claim 11, but does not teach wherein the FET comprises a FinFET device.
Kahya teaches a biosensor using a finFET on an SOI substrate (Fig. 1-9 and [0003] of Kahya). The semiconductor channel of the transistor is a fin shape structure on an SOI substrate (see Fig. 3a of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 16, Levon in view of Choi teaches all limitations of the FET device of claim 11, wherein the FET comprises a silicon on insulator device.
Kahya teaches a biosensor using a finFET on an SOI substrate (Fig. 1-9 and [0003] of Kahya). The semiconductor channel of the transistor is a fin shape structure on an SOI substrate (see Fig. 3a of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Claims 18-21, 26-29 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi and Cheng.
Regarding claim 18, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 overlapped with oxide layer 340), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the first metal; and
a second metal (control gate 346) in contact with the insulator; and
a floating gate (342) comprising the first metal and an extension (portion of floating gate 342 outside of oxide 344), wherein the extension is disposed to one side of the MIM structure (as shown in Fig. 3).
But Levon does not teach that the liner comprising a first metal, and wherein the extension comprises a well having a sensing surface at a bottom and sides of the well, and wherein the well is configured to contain a sample.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach that wherein the extension comprises a well having a sensing surface at a bottom and sides of the well, and wherein the well is configured to contain a sample.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of the well, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
The language of “configured to contain a sample” is functional description of the well. As combined, this is the function of the well in Cheng.
Regarding claim 19, Levon-Choi-Cheng teaches all limitations of the FET device of claim 1, but does not explicitly teach the FET device further comprising an additional layer covering the sensing surface, wherein the additional layer comprises a material selected from a group consisting of a conductive material and an insulating material.
In a different embodiment (Fig. 6 of Levon), Levon teaches an extension (625-640 in Fig. 6 of Levon) of the floating gate (615) that the sensing surface (top surface of 640) is covered by an additional layer (645), wherein the additional layer comprises an insulating material (glass as stated in [0049] of Levon).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed an additional layer as according to embodiment in Fig. 6 of Levon in order to have protect the sensing surface of Levon.
Regarding claim 20, Levon-Choi-Cheng teaches all limitations of the FET device of claim 18, and also teaches wherein the semiconductor channel comprises a silicon channel (see [0030] of Levon).
Regarding claim 21, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 overlapped with oxide layer 340), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the liner; and
a second metal (control gate 346) in contact with the insulator; and
a floating gate (342) comprising the first metal and an extension (portion of floating gate 342 outside of oxide 344), wherein the extension is disposed to one side of the MIM structure (as shown in Fig. 3).
But Levon does not teach that the liner comprising a first metal, and wherein the extension comprises a well having a sensing surface at a bottom, and wherein the well is configured to contain a sample and an additional layer covering the sensing surface.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach that wherein the extension comprises a well having a sensing surface at a bottom, and wherein the well is configured to contain a sample and an additional layer covering the sensing surface.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). An ILD (106 in Fig. 1) covers the sensing device with a well (112) in the ILD layer to expose a metal layer (M3). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of the well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of a well in an additional layer over the extension portion of the floating gate, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
The language of “configured to contain a sample” is functional description of the well. As combined, this is the function of the well in Cheng.
Regarding claim 26, Levon teaches a floating gate sensor (300 in Fig. 3 of Levon) comprising:
a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a gate structure comprising:
a liner (342) in contact with the first gate dielectric;
an insulator (oxide 344) in contact with the respective sidewalls and bottom well; and
a second electrode (control 346) in contact with the insulator; and
a floating gate extension (portion of floating gate 342 outside of oxide 344) disposed to one side of the gate structure and electrically connected to the liner, wherein the floating gate extension comprises a sensing surface (surface of sensing material 348) for sensing a sample in contact with the sensing surface (the phrase “for sensing…” is intended use of the sensing surface. As the label suggests, this surface is intended for sensing a sample).
But Levon does not teach that the liner is made of metal, and comprising respective sidewalls and a bottom well, the second electrode and the floating gate extension are made of metal.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach that the metal liner comprises respective sidewalls and a bottom well.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). An ILD (106 in Fig. 1) covers the sensing device with a well (112) in the ILD layer to expose a metal layer (M3). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of the well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of a well in an additional layer over the extension portion of the floating gate, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
Regarding claim 27, Levon-Choi-Cheng teaches all limitations of the floating gate sensor of claim 26, and further comprising an additional layer (ILD 106 of Cheng) covering the sensing surface.
Regarding claim 29, Levon-Choi-Cheng teaches all limitations of the floating gate sensor of claim 27, and also teaches wherein the additional layer comprises an insulating material (as taught in claim 27 above).
Regarding claim 27, Levon-Choi-Cheng teaches all limitations of the floating gate sensor of claim 26, and further comprising an additional layer (348 in Fig. 3 of Levon) covering the sensing surface.
Regarding claim 28, Levon-Choi-Cheng teaches all limitations of the floating gate sensor of claim 27, and also teaches wherein the additional layer comprises a conductive material (as described in [0030] of Levon).
Conclusion
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898