DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendment filed on 4/20/2026 is acknowledged. Claims 1, 11 and 18, 21, 26 have been amended.
Response to Arguments
Applicant's arguments filed 4/20/2026 have been fully considered but they are not persuasive.
Regarding claim 1-21, the Applicant contends that the proposed amendments have overcome the previous rejections of the claims. The Examiner respectfully disagrees.
The claim language of “a floating gate comprising the liner and a sensing surface” is very broad and open ended. Such open-endedness of the claim language allows the floating gate to include other elements between the liner and the sensing surface. Moreover, the claim language does not restrict the sensing surface to be a surface of the liner, and that the liner is a single material element. So the element 342 and 348 of the Fig. 3 of Levon meets the limitations of the floating gate as recited in the claims.
The rejection of claims 1-21 are therefore maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 recites “wherein the additional layer comprises a conductive material” in line 2. Claim 3 is dependent on claim 2, which defines that the “additional layer covering the sensing surface”. Claim 2 depends on claim 1, which requires “a sample in contact with the sensing surface”. However, if the conductive additional layer covering the sensing surface then how can any sample can come in contact with the sensing surface? For the purpose of examination, it is interpreted that the “additional layer” is the sensing surface that comes in contact with the sample.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7 and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Levon et al. (US 2005/0230271 A1) in view of Choi et al. (KR 101320687 B1).
Regarding claim 1, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 starting from the left end to the beginning point of the sensing material 348), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the liner; and
a second electrode (control gate 346) in contact with the insulator; and
a floating gate (the whole floating gate 342) comprising the liner (as defined above, the liner is a left part of the floating gate 342) and a sensing surface (upper surfaces of the sensing material layer 348, which includes a horizontal top surface and two vertical side surfaces), wherein the liner extends to the sensing surface (as defined above), and wherein the sensing surface is configured to sense a sample in contact with the sensing surface (the phrase “is configured to sense a sample” is a functional language, which only requires that the element is capable of performing the function, but not performing the exact function. As the label suggests, this surface is intended for sensing a sample).
But Levon does not teach that liner comprising a first metal; and the second electrode is a second metal.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
Regarding claim 2, Levon in view of Choi teaches all limitations of the FET device of claim 1, and further comprising an additional layer covering the sensing surface (please see interpretation in 112b rejection above, the sensing material 348 is the additional layer).
Regarding claim 3, Levon in view of Choi teaches all limitations of the FET device of claim 2, and also teaches wherein the additional layer comprises a conductive material (as described in [0030] of Levon).
Regarding claim 2, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach further comprising an additional layer covering the sensing surface.
In a different embodiment (Fig. 6 of Levon), Levon teaches an extension (625-640 in Fig. 6 of Levon) of the floating gate (615) that the sensing surface (top surface of 640) is covered by an additional layer (645), wherein the additional layer comprises an insulating material (glass as stated in [0049] of Levon).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed an additional layer as according to embodiment in Fig. 6 of Levon in order to have protect the sensing surface of Levon.
Regarding claim 4, Levon in view of Choi teaches all limitations of the FET device of claim 2, and also teaches wherein the additional layer comprises an insulating material (as stated in [0049] of Levon).
Regarding claim 7, Levon in view of Choi teaches all limitations of the FET device of claim 1, and also teaches wherein the FET comprises a planar device (as shown in Fig. 3 of Levon).
Regarding claim 10, Levon in view of Choi teaches all limitations of the FET device of claim 1, and also teaches wherein the semiconductor channel comprises a silicon channel (see [0030] of Levon).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, as applied in claim 1, and further in view of Cheng et al. (US 2016/0178568 A1).
Regarding claim 5, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach that the FET device further comprising a well having the sensing surface at a bottom and sides of the well, and wherein the well is configured to contain the sample.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of the well, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
Claims 6, 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, and further in view of Kahya (US 2010/0055699 A1).
Regarding claim 6, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach wherein the FET comprises a nanosheet device.
Kahya teaches a biosensor using a FET (Fig. 1-9 of Kahya). The semiconductor channel of the transistor is a nanosheet structure ([0002] of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 8, Levon in view of Choi teaches all limitations of the FET device of claim 1, but does not teach wherein the FET comprises a FinFET device.
Kahya teaches a biosensor using a finFET on an SOI substrate (Fig. 1-9 and [0003] of Kahya). The semiconductor channel of the transistor is a fin shape structure on an SOI substrate (see Fig. 3a of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 9, Levon in view of Choi teaches all limitations of the FET device of claim 1, and also teaches wherein the FET device comprises a silicon on insulator device ([0003] of Kahya).
Claims 11, 14 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi.
Regarding claim 11, Leon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 starting from the left end to the beginning point of the sensing material 348), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 340) in contact with the liner; and
a second electrode (control gate 346) in contact with the insulator;
a floating gate (the whole floating gate 342) comprising the liner (as defined above, the liner is a left part of the floating gate 342) and a sensing surface (upper surfaces of the sensing material layer 348, which includes a horizontal top surface and two vertical side surfaces), wherein the liner extends to the sensing surface (as defined above), and wherein the sensing surface is configured to sense a sample in contact with the sensing surface (the phrase “is configured to sense a sample” is a functional language, which only requires that the element is capable of performing the function, but not performing the exact function. As the label suggests, this surface is intended for sensing a sample).
But Levon does not teach that the liner comprising a first metal; and the second gate electrode is a second metal; and the FET device comprising: an additional layer covering the sensing surface, wherein the additional layer comprises a material selected from a group consisting of a conductive material and an insulating material.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach that the FET device comprising: an additional layer covering the sensing surface, wherein the additional layer comprises a material selected from a group consisting of a conductive material and an insulating material.
In a different embodiment (Fig. 6 of Levon), Levon teaches an extension (625-640 in Fig. 6 of Levon) of the floating gate (615) that the sensing surface (top surface of 640) is covered by an additional layer (645), wherein the additional layer comprises an insulating material (glass as stated in [0049] of Levon).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed an additional layer as according to embodiment in Fig. 6 of Levon in order to have protect the sensing surface of Levon.
Regarding claim 14, Levon in view of Choi teaches all limitations of the FET device of claim 11, and also teaches wherein the FET comprises a planar device (as shown in Fig. 3 of Levon).
Regarding claim 17, Levon in view of Choi teaches all limitations of the FET device of claim 11, and also teaches wherein the semiconductor channel comprises a silicon channel (see [0030] of Levon).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, and further in view of Cheng et al. (US 2016/0178568 A1).
Regarding claim 12, Levon in view of Choi teaches all limitations of the FET device of claim 11, but does not teach wherein the floating gate comprises a well having the sensing surface at a bottom and sides of the well, wherein the well is configured to contain the sample.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of the well, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
Claims 13, 15, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi, and further in view of Kahya.
Regarding claim 13, Levon in view of Choi teaches all limitations of the FET device of claim 11, but does not teach wherein the FET comprises a nanosheet device.
Kahya teaches a biosensor using a FET (Fig. 1-9 of Kahya). The semiconductor channel of the transistor is a nanosheet structure ([0002] of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 15, Levon in view of Choi teaches all limitations of the FET device of claim 11, but does not teach wherein the FET comprises a FinFET device.
Kahya teaches a biosensor using a finFET on an SOI substrate (Fig. 1-9 and [0003] of Kahya). The semiconductor channel of the transistor is a fin shape structure on an SOI substrate (see Fig. 3a of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Regarding claim 16, Levon in view of Choi teaches all limitations of the FET device of claim 11, wherein the FET comprises a silicon on insulator device.
Kahya teaches a biosensor using a finFET on an SOI substrate (Fig. 1-9 and [0003] of Kahya). The semiconductor channel of the transistor is a fin shape structure on an SOI substrate (see Fig. 3a of Kahya).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed the semiconductor channel of Levon as a nanosheet in order to increase the performance of the transistor.
Claims 18-21 are rejected under 35 U.S.C. 103 as being unpatentable over Levon in view of Choi and Cheng.
Regarding claim 18, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 starting from the left end to the beginning point of the sensing material 348), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the liner; and
a second electrode (control gate 346) in contact with the insulator; and
a floating gate (342) comprising the liner (as defined above, the liner is a left part of the floating gate 342) and a sensing surface (upper surfaces of the sensing material layer 348, which includes a horizontal top surface and two vertical side surfaces), wherein the liner extends to the sensing surface (as defined above).
But Levon does not teach that the liner comprising a first metal; the second electrode is a second metal; and wherein the sensing surface comprises a well having a bottom surface and side surfaces, and wherein the well is configured to contain a sample.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach that wherein the sensing surface comprises a well having a bottom surface and side surfaces, and wherein the well is configured to contain a sample.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of a well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of the well, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
The language of “configured to contain a sample” is functional description of the well. As combined, this is the function of the well in Cheng.
Regarding claim 19, Levon-Choi-Cheng teaches all limitations of the FET device of claim 1, but does not explicitly teach the FET device further comprising an additional layer covering the sensing surface, wherein the additional layer comprises a material selected from a group consisting of a conductive material and an insulating material.
In a different embodiment (Fig. 6 of Levon), Levon teaches an extension (625-640 in Fig. 6 of Levon) of the floating gate (615) that the sensing surface (top surface of 640) is covered by an additional layer (645), wherein the additional layer comprises an insulating material (glass as stated in [0049] of Levon).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have formed an additional layer as according to embodiment in Fig. 6 of Levon in order to have protect the sensing surface of Levon.
Regarding claim 20, Levon-Choi-Cheng teaches all limitations of the FET device of claim 18, and also teaches wherein the semiconductor channel comprises a silicon channel (see [0030] of Levon).
Regarding claim 21, Levon teaches a field effect transistor (FET) device (300 in Fig. 3 of Levon) comprising:
a FET (transistor with S/D 320-330) comprising a semiconductor channel (region of substrate overlapped by oxide layer 340);
a first gate dielectric (oxide 340) in contact with the semiconductor channel;
a metal-insulator-metal (MIM) structure (342-346) comprising:
a liner (portion of floating gate 342 starting from the left end to the beginning point of the sensing material 348), wherein the liner is in contact with the first gate dielectric (as shown in Fig. 3);
an insulator (oxide 344) in contact with the liner; and
a second electrode (control gate 346) in contact with the insulator;
a floating gate (the entire floating gate 342) comprising the liner (as defined above, the liner is left portion of the floating gate 342) and a sensing surface (upper surfaces of the sensing material layer 348, which includes a horizontal top surface and two vertical side surfaces), wherein the liner extends to the sensing surface (as shown in Fig. 3).
But Levon does not teach the liner comprising a first metal; and the second electrode is a second metal; and wherein the sensing surface comprises a well, and wherein the well is configured to contain a sample; and an additional layer covering the sensing surface.
Choi teaches a biosensor using a FET (Figs. 1a-1b of Choi). The control gate and floating gate are formed using a metal (see [0021] of Choi).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the floating gate and second electrode of Levon from metals in order to have higher conductivity.
But Levon in view of Choi does not teach that wherein the sensing surface comprises a well, and wherein the well is configured to contain a sample; and an additional layer covering the sensing surface.
Cheng teaches a biosensing FET (100 in Fig. 1 of Cheng). An ILD (106 in Fig. 1) covers the sensing device with a well (112) in the ILD layer to expose a metal layer (M3). The sensing surface comprises a horizontal surface (112h in Fig. 1) is located at the bottom of the well (112) and vertical side surfaces (112v) of the well.
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have made the sensing surface at a bottom and sides of a well in an additional layer over the extension portion of the floating gate, as disclosed by Cheng, in order to increase the sensing surface and thereby increase the sensed signal.
The language of “configured to contain a sample” is functional description of the well. As combined, this is the function of the well in Cheng.
Allowable Subject Matter
Claims 26-29 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 26, the prior art of record does not disclose or fairly suggests “a gate structure comprising: a metal liner comprising a first metal and having respective sidewalls and a bottom surface in contact with the first gate dielectric; an insulator in contact with the respective sidewalls and the bottom surface; and a second metal in contact with the insulator; and a floating gate comprising a sensing surface disposed to one side of the gate structure, wherein the metal liner extends to the sensing surface, and wherein the sensing surface is configured to sense a sample in contact with the sensing surface” along with other limitations of the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN A HOANG whose telephone number is (571)270-0406. The examiner can normally be reached Monday-Friday 8-9am, 10am-6pm EST.
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/Tuan A Hoang/ Primary Examiner, Art Unit 2898
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