Prosecution Insights
Last updated: October 04, 2026
Application No. 18/307,055

WIRING SUBSTRATE

Non-Final OA §103
Filed
Apr 26, 2023
Priority
May 19, 2022 — JP 2022-082263
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Ibiden Co., Ltd.
OA Round
5 (Non-Final)
78%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
698 granted / 893 resolved
+10.2% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
43 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.4%
-6.6% vs TC avg
§102
47.0%
+7.0% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 893 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on August 26, 2026 has been entered. Response to Arguments Applicant's arguments with respect to claims 1 – 20 have been considered, but are moot in view of the new ground(s) of rejection. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nishioka et al. (U.S. Patent No. 10,368,438) in view of Jeong et al. (U.S. Patent Publication No. 2022/0077078), and further in view of Tapacio et al. (U.S. Patent Publication No. 2009/0278264). Regarding claim 1, in Figure 1, Nishioka discloses a wiring substrate, comprising: a core substrate (10); a build-up part (20) formed on a surface of the core substrate and comprising a plurality of insulating layers (21, 24, 30) and a plurality of conductor layers (22, 25, 26, 27, 28, S1, S2); and a covering insulating layer (30) comprising a photosensitive resin (col. 5, lines 22 – 30 and col. 13, lines 14 – 18) and formed on the build-up part such that the covering insulating layer is covering an outermost surface of the build-up part, wherein the build-up part is formed such that the plurality of insulating layers includes a first insulating layer (24) comprising a thermosetting resin and an inorganic filler (col. 4, lines 30 – 40) and forming an outermost one of the insulating layers, that the plurality of conductor layers includes a first conductor layer (26) formed on a surface of the first insulating layer and including a first conductor pad (28) formed in a substantially rectangular planar shape and in direct contact with the surface of the first insulating layer, and that an elongation rate of the first insulating layer is greater than an elongation rate of each of the other insulating layers in the build-up part, and the covering insulating layer is formed on the first insulating layer of the build-up part such that the covering insulating layer has an opening (34) entirely exposing an upper surface and a side surface of the first conductor pad (the upper surface and side surfaces of conductor pad 28 are exposed; similar to the upper surface and side surfaces of conductor pad P1 being exposed from the covering insulating layer 110 in Figure 1 of the claimed invention). Nishioka does not specifically disclose an elongation rate of the first insulating layer being greater than an elongation rate of each of the insulating layers other than the first insulating layer in the build-up part, and the first conductor pad 28 being formed in a substantially rectangular planar shape. However, Jeong teaches an outermost layer 111a including an insulating resin having a greater elongation than the other insulating layers (111b) stacked thereon (Figure 3B, paragraphs [0025] and [0039]; in Figure 3B, the substrate 110 may include one or more first insulating layers 111a, paragraph [0040], thus there may be a single outermost layer 111a). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the elongation rate of the outermost insulating layer 24 of Nishioka to be greater than the elongation rate of the other insulating layers 21 stacked thereon as taught by Jeong so as to improve the mechanical strength of the outermost insulating layer 24. Further, in Figures 3 and 6, Tapacio teaches a conductor pad 50’ that connects to bump 40 being formed in a substantially rectangular planar shape (claim 21). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for conductor pad 28 of Nishioka to be formed in a substantially rectangular planar shape as taught by Jeong modified by Nishioka in order for the conductor pad 28 to provide more surface area for the connection to solder bump S2. Regarding claim 2, Nishioka discloses wherein the build-up part is formed such that the first conductor pad of the first conductor layer is not directly connected to another pad in the first conductor layer or a wiring in the first conductor layer (Figure 1). Regarding claim 3, Nishioka discloses wherein the build-up part is formed such that the elongation rate of the first insulating layer is 1.5% or greater (Figure 1). Regarding claim 4, Nishioka discloses wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.17 or less at a frequency of 5.8 GHz (Figure 1). Regarding claim 5, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1). Regarding claim 6, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1). Regarding claim 7, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1). Regarding claim 8, Nishioka discloses wherein the build-up part is formed such that the elongation rate of the first insulating layer is 1.5% or greater (Figure 1). Regarding claim 9, Nishioka discloses wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.17 or less at a frequency of 5.8 GHz (Figure 1). Regarding claim 10, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1). Regarding claim 11, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1). Regarding claim 12, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1). Regarding claim 13, Nishioka discloses wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.17 or less at a frequency of 5.8 GHz (Figure 1). Regarding claim 14, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1). Regarding claim 15, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1). Regarding claim 16, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1). Regarding claim 17, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1). Regarding claim 18, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1). Regarding claim 19, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1). Regarding claim 20, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Show 6 earlier events
Dec 04, 2025
Response after Non-Final Action
Dec 17, 2025
Final Rejection mailed — §103
Apr 15, 2026
Response after Non-Final Action
Apr 30, 2026
Final Rejection mailed — §103
Jul 10, 2026
Response after Non-Final Action
Aug 26, 2026
Request for Continued Examination
Aug 31, 2026
Response after Non-Final Action
Sep 10, 2026
Non-Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.2%)
2y 6m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 893 resolved cases by this examiner. Grant probability derived from career allowance rate.

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