DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments with respect to claims 1 – 20 have been considered. In light of the arguments, Examiner has withdrawn the Final Rejection dated December 17, 2025 and is providing a different interpretation of the prior art reference in this new Final Rejection. Please see the ground(s) of rejection below.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Nishioka et al. (U.S. Patent No. 10,368,438) in view of Jeong et al. (U.S. Patent Publication No. 2022/0077078).
Regarding claim 1, in Figure 1, Nishioka discloses a wiring substrate, comprising: a core substrate (10); a build-up part (20) formed on a surface of the core substrate and comprising a plurality of insulating layers (21, 24, 30) and a plurality of conductor layers (22, 25, 26, 27, 28, S1, S2); and a covering insulating layer (30) comprising a photosensitive resin (col. 5, lines 22 – 30 and col. 13, lines 14 – 18) and formed on the build-up part such that the covering insulating layer is covering an outermost surface of the build-up part, wherein the build-up part is formed such that the plurality of insulating layers includes a first insulating layer (24) comprising a thermosetting resin and an inorganic filler (col. 4, lines 30 – 40) and forming an outermost one of the insulating layers, that the plurality of conductor layers includes a first conductor layer (26) formed on a surface of the first insulating layer and including a first conductor pad (28) in direct contact with the surface of the first insulating layer, and that an elongation rate of the first insulating layer is greater than an elongation rate of each of the other insulating layers in the build-up part, and the covering insulating layer is formed on the first insulating layer of the build-up part such that the covering insulating layer has an opening (34) entirely exposing an upper surface and a side surface of the first conductor pad (the upper surface and side surfaces of conductor pad 28 are exposed; similar to the upper surface and side surfaces of conductor pad P1 being exposed from the covering insulating layer 110 in Figure 1 of the claimed invention). Ikeda does not specifically disclose an elongation rate of the first insulating layer being greater than an elongation rate of each of the insulating layers other than the first insulating layer in the build-up part. However, Jeong teaches an outermost layer 111a including an insulating resin having a greater elongation than the other insulating layers (111b) stacked thereon (Figure 3B, paragraphs [0025] and [0039]; in Figure 3B, the substrate 110 may include one or more first insulating layers 111a, paragraph [0040], thus there may be a single outermost layer 111a).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention for the elongation rate of the outermost insulating layer 24 of Nishioka to be greater than the elongation rate of the other insulating layers 21 stacked thereon as taught by Jeong so as to improve the mechanical strength of the outermost insulating layer 24.
Regarding claim 2, Nishioka discloses wherein the build-up part is formed such that the first conductor pad of the first conductor layer is not directly connected to another pad in the first conductor layer or a wiring in the first conductor layer (Figure 1).
Regarding claim 3, Nishioka discloses wherein the build-up part is formed such that the elongation rate of the first insulating layer is 1.5% or greater (Figure 1).
Regarding claim 4, Nishioka discloses wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.17 or less at a frequency of 5.8 GHz (Figure 1).
Regarding claim 5, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1).
Regarding claim 6, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1).
Regarding claim 7, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1).
Regarding claim 8, Nishioka discloses wherein the build-up part is formed such that the elongation rate of the first insulating layer is 1.5% or greater (Figure 1).
Regarding claim 9, Nishioka discloses wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.17 or less at a frequency of 5.8 GHz (Figure 1).
Regarding claim 10, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1).
Regarding claim 11, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1).
Regarding claim 12, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1).
Regarding claim 13, Nishioka discloses wherein the build-up part is formed such that the first insulating layer has a dielectric loss tangent of 0.17 or less at a frequency of 5.8 GHz (Figure 1).
Regarding claim 14, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1).
Regarding claim 15, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1).
Regarding claim 16, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1).
Regarding claim 17, Nishioka discloses a second build-up part formed on a second surface of the core substrate on an opposite side with respect to the surface on which the build-up part is formed, wherein the second build-up part is formed such that the second build-up part includes a plurality of insulating layers and that a number of the insulating layers in the second build-up part is equal to a number of the insulating layers in the build-up part (Figure 1).
Regarding claim 18, Nishioka discloses wherein the second build-up part is formed such that the first insulating layer in the build-up part and an outermost insulating layer in the second build-up part are formed of a same material (Figure 1).
Regarding claim 19, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1).
Regarding claim 20, Nishioka discloses wherein the build-up part is formed such that the plurality of conductor layers includes a second conductor layer formed on an opposite side with respect to the first conductor layer via the first insulating layer and that the build-up part includes a via conductor penetrating through the first insulating layer and connecting the second conductor layer and the first conductor pad of the first conductor layer (Figure 1).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST.
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TREMESHA W. BURNS
Primary Examiner
Art Unit 2847
/TREMESHA W BURNS/Primary Examiner, Art Unit 2847
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