DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II, Species II (Fig. 8), (claims 1-14) in the reply filed on 09/04/2025 is acknowledged. Based on amendment on 02/25/2026 claims 1 and 10 recite “encapsulating .. a portion of the semiconductor die and the rigid-flex sub-assembly” which do not read on originally elected species II of Fig. 8 rather read on non-elected species of Fig. 9. Therefore these claims will be examined based on elected species of Fig. 8 as completely encapsulating as shown in Fig. 8.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/04/25.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the limitation in claims 4, 14 “encapsulating a portion of the first component or the component..” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
While applicant’s arguments on 02/25/2026 regarding claims 1 and 10 for drawing objection are persuasive in view of the amendment filed on 02/25/2026 but still not persuasive for claims 10 and 14 and none of the Figures shown these limitations.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1 and 10 recite “encapsulating .. a portion of the semiconductor die and the rigid-flex sub-assembly” are indefinite as they do not read on originally elected species II of Fig. 8 rather read on non-elected species of Fig. 9. Therefore these claims will be examined based on elected species of Fig. 8 as completely encapsulating as shown in Fig. 8.
Claims 4, 14 recite 4 “encapsulating at least a portion of the first component” is unclear what’s been shown in Fig. 8. As shown the encapsulant 602 completely encapsulating the semiconductor die 302, the rigid-flex sub assembly 102, the first component 202.Claim language like “completely encapsulating” is suggested.
Claims 2-9, 11-14 are also rejected being dependent on rejected claims, 10.
Claims 1, 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are limitations of claims 7 and 11. As disclosed in Fig. 8 the final product is formed using the steps shown in Fig. 6 -Fig. 7 by removing the carrier substrate 306 in forming RDL structure 702 to connect to external devices. The method steps of claims 1 and 10 are the intermediate steps of an intermediate structure of Fig. 6 which has no use or enabled to do any function.
Claims 2-9, 11-14 are also rejected being dependent on rejected claims 1, 10.
Applicant’s arguments on 02/25/2026 are not found persuasive as mentioned previously the method steps of claims 1 and 10 are the intermediate steps of an intermediate structure of Fig. 6 which has no use or enabled to do any function and the final product of Fig. 8 does not have the carrier substrate which has been removed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 10, 12 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2016/0005714 A1) in view of Cha et al. (US PGPUB 2004/0150107 A1).
Regarding claims 1, 10: Lee teaches in Fig. 2, 14A-14C about a method comprising:
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placing a semiconductor die 20 on a carrier substrate 10 (Fig. 14A, as it supports/carry 20);
affixing a rigid-flex sub-assembly 50 on the semiconductor die, the rigid-flex sub- assembly comprising:
a rigid portion (the portion in CR region/middle region and as it is not bended therefore interpreting as rigid [0065])); and
a flex portion (the portion in IR region) including a conductive trace 57;
after affixing the rigid-flex sub-assembly on the semiconductor die, bending a distal region of the flex portion such that the bent distal region is not coplanar with the rigid portion (as shown in Fig. 2, 14C, IR portion of 50 is bended with respect to CR portion of 50 and no coplanar); and
encapsulating with an encapsulant 70 a portion of the semiconductor die and the rigid-flex sub-assembly (Fig. 2).
Lee does not explicitly show in this embodiment of Fig. 14A-14C about how to bend (bending) a distal region of the flex portion such that the bent distal region is not coplanar with the rigid portion and after affixing the rigid-flex sub-assembly on the semiconductor die, bending a distal region of the flex portion.
However Lee teaches in other embodiments of Fig. 12A-12C and 13A-13D about ways to bend a distal region of the flex portion (IR portion) such that the bent distal region is not coplanar with the rigid portion (CR portion). Furthermore Cha teaches in Fig. 5c to 5d about after affixing the rigid-flex sub-assembly 120 on the semiconductor die 6, bending a distal region 122 of the flex portion.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the application was filed, to have the feature of bending the distal end before or after affixing the assembly according to the teaching of Lee and Cha, since it has been held that choosing from a finite number of identified, predictable solutions such as bending the distal end before or after to make further electrical connection to stacked semiconductor package (Cha, abstract).
Regarding claims 2, 12: Lee teaches in Fig. 2 wherein the rigid-flex sub-assembly further includes a plurality of connection pads (59’s or bottom 57’s), at least one of the connection pads conductively connected to the conductive trace (upper 57’s).
Claims 3-6, 8, 13-14 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2016/0005714 A1) and Cha et al. (US PGPUB 2004/0150107 A1) and further in view of Wang et al (US Patent 11,094,634 B2)).
Regarding claims 3, 13: Lee teaches in Fig. 2 affixing a first component 62/64 on the rigid-flex sub-assembly 50, a conductive pad 72a/72b of the first component conductively connected to the conductive trace.
Lee does not explicitly show the first component conductively connected to the conductive trace.
However Lee teaches in [0073] – [0074] about the first component 62/64 may be electrically connected to the upper package 50 (the rigid-flex assembly). Wang also teaches in Fig. 5 about how first/upper components 102/240 can be conductively connected to the conductive trace 126 of rigid-flex assembly 120a via conductive traces CT’s and conductive vias CV’s (Fig. 2B).
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to use well known technique of interconnecting upper and lower components using conductive traces/pads and vias for electrical connection.
Regarding claims 4, 14: Lee teaches in Fig. 2 wherein encapsulating with the encapsulant 70 further includes encapsulating at least a portion of the first component 62/64.
Regarding claim 5: Lee teaches in wherein the first component affixed on the rigid-flex sub- assembly is characterized as a second semiconductor die [0072].
Regarding claim 6: Lee teaches in [0072] affixing a second component 62/64 on the rigid- flex sub-assembly, the second component characterized as a passive component (as no specific type is claimed in BRI logic/memory chip can be considered passive in compare to control chip/CPU).
Regarding claim 8: Lee does not explicitly talk about wherein the rigid portion is formed from non-conductive epoxy prepreg and FR4 materials.
Wang teaches in col. 4, lines 10-20 about wherein the rigid portion is formed from non-conductive epoxy prepreg and FR4 materials.
It would have been obvious to one of ordinary skill in the art at the time of the invention was made to have the material as claimed, since it has been held to be within the general skill of a worker in the art to select a known material FR4 on the basis of its suitability for the intended use for rigidity as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claims 11 are rejected under 35 U.S.C. 103 as being obvious over Lee et al (US 2016/0005714 A1), Cha et al. (US PGPUB 2004/0150107 A1) and further in view of Yoo et al. (US PGPUB 2019/0115286 A1) and further in view of Jeon et al. (US Patent 11705341 B2)
Regarding claim 11: Lee does not teach removing the carrier substrate to expose die pads of the semiconductor die and conductive surface of the bent distal region of the flex portion; and forming a first redistribution layer (RDL) substrate over the exposed die pads of the semiconductor die and conductive surface of the of the bent distal region.
Yoo teaches in Fig. 7 and [0034] removing the carrier substrate 201 to expose die pads of the semiconductor die and conductive surface of the bent distal region of the flex portion.
Yoo further teaches in [0034] forming a first redistribution layer (RDL) substrate over the exposed die pads of the semiconductor die and conductive surface of the of the bent distal region. ( For clarification Yoo teaches in [0034] about after removing the second portion 220B of the flexible member 220 may be used to selectively connect the semiconductor device assembly 200′, and more specifically the semiconductor device(s) 210, to an external device or assembly via the connector 240 and it is well known in the art to use redistribution layer structure including pads/conductive traces/solder balls etc. to connect to the external device as Jeon shows in Fig. 1Q-1R forming a first redistribution layer (RDL) substrate (400+410) over the exposed die pads of the semiconductor die and conductive surface of 100 to connect to further external devices.
Therefore it would have been obvious to one of ordinary skill in the art, at the time of applicant’s invention to use the teachings of Yoo and Jeon to use and remove of an intermediate carrier substrate and connect another PCB or external device (for example Lee’s lower package 100 as the final device using redistribution layer to connect as a design choice of intended application (Yoo, [0035])
Claims 1-2, 9 are rejected under 35 U.S.C. 103 as being obvious over Yoo et al. (US PGPUB 2019/0115286 A1) in view of Lee et al (US 2016/0005714 A1) and Cha et al. (US PGPUB 2004/0150107 A1).
Regarding claim 1: Yoo teaches in Fig. 4-7 about a method comprising:
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placing a semiconductor die 210 on a carrier substrate 201;
affixing a rigid-flex sub-assembly 220 on the semiconductor die, the rigid-flex sub- assembly comprising:
a rigid portion 220A; and
a flex portion 220B including a conductive trace 224;
after affixing the rigid-flex sub-assembly on the semiconductor die, bending a distal region of the flex portion such that the bent distal region is not coplanar with the rigid portion; and
encapsulating with an encapsulant 250 at least a portion of the semiconductor die 210 and the rigid-flex sub-assembly 220.
Yoo does not explicitly show bending a distal region of the flex portion such that the bent distal region is not coplanar with the rigid portion and after affixing the rigid-flex sub-assembly on the semiconductor die, bending a distal region of the flex portion.
However Yoo teaches in [0023], [0032] about the connector 240 at the distal end of the flexible and bendable member 220 to connect and disconnect from an externa assembly.
Lee further teaches in other embodiments of Fig. 12A-12C and 13A-13D about ways to bend a distal region of the flex portion (IR portion) such that the bent distal region is not coplanar with the rigid portion (CR portion). Moreover Cha teaches in Fig. 5c to 5d about after affixing the rigid-flex sub-assembly 120 on the semiconductor die 6, bending a distal region 122 of the flex portion.
Thus, it would have been obvious to try by one of ordinary skill in the art, at the time the application was filed, to have the feature of bending the distal end before or after affixing the assembly according to the teaching of Lee and Cha, since it has been held that choosing from a finite number of identified, predictable solutions such as bending the distal end before or after to make further electrical connection to stacked semiconductor package (Cha, abstract).
Regarding claim 2: Yoo teaches in Fig. 1 wherein the rigid-flex sub-assembly further includes a plurality of connection pads (123), at least one of the connection pads conductively connected to the conductive trace (124).
Regarding claim 9: Yoo teaches in Fig. 1, [0021] wherein the flex portion 120 includes the conductive trace 124 formed on a flexible non-conductive material [0021].
Claim 7 is rejected under 35 U.S.C. 103 as being obvious over Yoo et al. (US PGPUB 2019/0115286 A1) in view of Lee et al (US 2016/0005714 A1), Cha et al. (US PGPUB 2004/0150107 A1) and further in view of Jeon et al. (US Patent 11705341 B2)
Regarding claim 7: Yoo teaches in Fig. 7 and [0034] removing the carrier substrate 201 to expose die pads of the semiconductor die and conductive surface of the bent distal region of the flex portion; and forming a first redistribution layer (RDL) substrate over the exposed die pads of the semiconductor die and conductive surface of the of the bent distal region.
Yoo does not explicitly show forming a first redistribution layer (RDL) substrate over the exposed die pads of the semiconductor die and conductive surface of the of the bent distal region.
However Yoo teaches in [0034] about after removing the second portion 220B of the flexible member 220 may be used to selectively connect the semiconductor device assembly 200′, and more specifically the semiconductor device(s) 210, to an external device or assembly via the connector 240 and it is well known in the art to use redistribution layer structure including pads/conductive taces/solder balls etc. to connect to the external device as Jeon shows in Fig. 1Q-1R forming a first redistribution layer (RDL) substrate (400+410) over the exposed die pads of the semiconductor die and conductive surface of 100 to connect to further external devices.
Response to Arguments
Applicant’s arguments see pages 1-5, filed on 02/25/2026, with respect to the rejection(s) of claims 1, 4, 10, 14 under 103 and 112 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of new prior art Cha et al. (US PGPUB 2004/0150107 A1)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED SHAMSUZZAMAN whose telephone number is (571)270-1839. The examiner can normally be reached Monday-Friday 7 am -4 pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Mohammed Shamsuzzaman/Primary Examiner, Art Unit 2897
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