Prosecution Insights
Last updated: October 02, 2026
Application No. 18/307,101

STRUCTURAL ENCLOSURE FOR PROTECTION AGAINST FOREIGN OBJECT DEBRIS

Final Rejection §102§103
Filed
Apr 26, 2023
Examiner
MOJADDEDI, OMAR F
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
RAYTHEON Company
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
481 granted / 538 resolved
+21.4% vs TC avg
Moderate +10% lift
Without
With
+10.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
63 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
2.0%
-38.0% vs TC avg
§103
53.8%
+13.8% vs TC avg
§102
25.9%
-14.1% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Status of Claims 1. Applicant's amendment of claims 1, 4, 8-10, 13, and 17-19 in “Claims - 07/15/2026” with “Amendment/Req. Reconsideration-After Non-Final Reject - 07/15/2026”, have been acknowledged by Examiner. This office action considers claims 1-20 pending for prosecution. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 2. Claims 1, 8-9, 10, and 17-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sunohara (US 20110080713 A1; hereinafter Sunohara). Regarding claim 1, Sunohara teaches a system (see the entire document, specifically Fig. 1+; [0004+], and as cited below) comprising (see alternative rejection for claim 1 below): a substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]); an electrical component (1; Fig. 4; [0058, 0046-0047]) mounted to the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]), the electrical component (1; Fig. 4; [0058, 0046-0047]) comprising multiple non-collapsible solder columns (45; Fig. 1; [0044]; solder bump) physically and electrically connecting the electrical component (1; Fig. 4; [0058, 0046-0047]) to the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]); and a structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) positioned around lateral edges of the electrical component (1; Fig. 4; [0058, 0046-0047]) and mounted to the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]), the structural enclosure ({3, 3b}; Fig. 4 in view of Fig. 3; [0046-0048]) comprising raised walls ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) extending away from the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]) and surrounding the electrical component (1; Fig. 4; [0058, 0046-0047]), the raised walls ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) (see below for “configured to block foreign object debris from”) contacting the non-collapsible solder columns (45; Fig. 1; [0044]; solder bump). In regards “the raised walls configured to block foreign object debris from contacting the non-collapsible solder columns” (emphasis added), per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Sunohara teaches the structure of claim 1 as detailed above. Thus, Sunohara teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 8, Sunohara teaches all of the features of claim 1. Sunohara further teaches wherein: the electrical component (1; Fig. 4; [0058, 0046-0047]; logic chip) comprises a processor; the non-collapsible solder columns (45; Fig. 1; [0044]; solder bump) form a column grid array (see Fig. 1); and the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]; motherboard) comprises a printed circuit board. Regarding claim 9, Sunohara teaches all of the features of claim 1. Sunohara further teaches wherein: the non-collapsible solder columns (45; Fig. 1; [0044]; solder bump) are surface-mounted to a surface of the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]); and the structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) is attached to the surface of the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]). Regarding claim 10, Sunohara teaches a method (see the entire document, specifically Fig. 1+; [0004+], and as cited below) comprising (see alternative rejection for claim 10 below): obtaining an electrical component (1; Fig. 4; [0058, 0046-0047]) mounted to a substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]), the electrical component (1; Fig. 4; [0058, 0046-0047]) comprising multiple non-collapsible solder columns (45; Fig. 1; [0044]; solder bump) physically and electrically connecting the electrical component (1; Fig. 4; [0058, 0046-0047]) to the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]); and attaching a structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) to the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]) such that the structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) is positioned around lateral edges of the electrical component (1; Fig. 4; [0058, 0046-0047]), the structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) comprising raised walls ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) extending away from the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]) and surrounding the electrical component (1; Fig. 4; [0058, 0046-0047]), the raised walls ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) (see below for “configured to block foreign object debris from”) contacting the non-collapsible solder columns (45; Fig. 1; [0044]; solder bump). In regards “the raised walls configured to block foreign object debris from contacting the non-collapsible solder columns” (emphasis added), per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Sunohara teaches the structure of claim 1 as detailed above. Thus, Sunohara teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 17, Sunohara teaches all of the features of claim 10. Sunohara further teaches wherein: the electrical component (1; Fig. 4; [0058, 0046-0047]; logic chip) comprises a processor; the non-collapsible solder columns (45; Fig. 1; [0044]; solder bump) form a column grid array (see Fig. 1); and the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]; motherboard) comprises a printed circuit board. Regarding claim 18, Sunohara teaches all of the features of claim 10. Sunohara further teaches wherein: the non-collapsible solder columns (45; Fig. 1; [0044]; solder bump) are surface-mounted to a surface of the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]); and the structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) is attached to the surface of the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]). Regarding claim 19, Sunohara teaches an apparatus (see the entire document, specifically Fig. 1+; [0004+], and as cited below) comprising (see alternative rejection for claim 19 below): a structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) configured to be mounted to a substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]) and positioned around lateral edges of an electrical component (1; Fig. 4; [0058, 0046-0047]) mounted to the substrate ({10, 16, 6}; Fig. 4; [0030-0031, 0049-0050]); wherein the structural enclosure ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) comprises raised walls ({3b}; Fig. 4 in view of Fig. 3; [0046-0048]) configured to surround the electrical component (1; Fig. 4; [0058, 0046-0047]) (see below for “configured to block foreign object debris from”) contacting non-collapsible solder columns (in view of 45; Figs. 2, 4 [0045]) of the electrical component (1; Fig. 4; [0058, 0046-0047]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document. 3. Claims 1-5, 7, 9, 10-14, 16, 18, and 19-20 are rejected under 35 U.S.C.103 as being unpatentable over Uhlig et al. (US 20210305109 A1; hereinafter Uhlig), in view of Sunohara (US 20110080713 A1; hereinafter Sunohara). Regarding claim 1, Uhlig teaches a system (see the entire document, specifically Fig. 1+; [0010+], and as cited below) comprising (see alternative rejection for claim 1 above): a substrate (118; Fig. 1; [0079-0080]); an electrical component (102; Fig. 1; [0073, 0080]) mounted to the substrate (118; Fig. 1; [0079-0080]), the electrical component (102; Fig. 1; [0073, 0080]) comprising (see below for “multiple non-collapsible solder columns”) (see [0080-0081]; electronic component 102 may be soldered on the carrier 118) physically and electrically connecting the electrical component to the substrate (118; Fig. 1; [0079-0080]); and a structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) positioned around lateral edges of the electrical component (102; Fig. 1; [0073, 0080]) and mounted to the substrate (118; Fig. 1; [0079-0080]), the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) comprising raised walls ({112}; Fig. 1; [0073-0074, 0083]) extending away from the substrate (118; Fig. 1; [0079-0080]) and surrounding the electrical component (102; Fig. 1; [0073, 0080]), the raised walls {112}; Fig. 1; see [0074]) (see below for “configured to block foreign object debris from”) contacting the (see below for “non-collapsible solder columns”) (see [0080-0081]; electronic component 102 may be soldered on the carrier 118). As noted above, Uhlig does not expressly disclose “the electrical component comprising multiple non-collapsible solder columns physically and electrically connecting the electrical component to the substrate” and “the raised walls configured to block foreign object debris from contacting the non-collapsible solder columns”. However, in the analogous art, Sunohara teaches a wiring board for use in mounting an electronic component such as a semiconductor element (chip) thereon ([0002]), wherein (Fig. 1+; [0090+]) a chip (1; Fig. 2; [0042]) is physically and electrically connected to wiring board (10) through solder balls (45; Figs. 2, 4 [0045]) It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Sunohara’s solder balls connection layer into Uhlig’s device, and thereby, modified Uhlig’s (by Sunohara) device will have an electrical component (102; Fig. 1; [0073, 0080]) mounted to the substrate (118; Fig. 1; [0079-0080]), the electrical component (102; Fig. 1; [0073, 0080]) comprising multiple non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]) physically and electrically connecting the electrical component to the substrate (118; Fig. 1; [0079-0080]); and a structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) positioned around lateral edges of the electrical component (102; Fig. 1; [0073, 0080]) and mounted to the substrate (118; Fig. 1; [0079-0080]), the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) comprising raised walls ({112}; Fig. 1; [0073-0074, 0083]) extending away from the substrate (118; Fig. 1; [0079-0080]) and surrounding the electrical component (102; Fig. 1; [0073, 0080]), the raised walls ({112}; Fig. 1; see [0074]) (see below for “configured to block foreign object debris from”) contacting the non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]). The ordinary artisan would have been motivated to modify Uhlig in the manner set forth above, at least, because this inclusion provides multiple solder balls to connect the chip to the substrate (Sunohara [0045]), which provides multiple solder structures between the chip and substrate which helps increase the reliability of the electrical connection. In regards “the raised walls configured to block foreign object debris from contacting the non-collapsible solder columns” (emphasis added), per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, modified Uhlig (by Sunohara) teaches the structure of claim 1 as detailed above. Thus, modified Uhlig (by Sunohara) teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 2, modified Uhlig (by Sunohara) teaches all of the features of claim 1. Modified Uhlig (by Sunohara) further teaches wherein: the electrical component (102; Fig. 1; [0073, 0080]) further comprises a semiconductor die (102; Fig. 1; [0073, 0080]) and a lid (152; Fig. 1; [0072-0075]), the lid (152; Fig. 1; [0072-0075]) in thermal contact (see [0027, 0042, 0074], where 110 is a soft encapsulant ([0074]), and an equilibration of thermal load may be balanced out by such a soft encapsulant [0042])) with the semiconductor die (102; Fig. 1; [0073, 0080]); and the structural enclosure ({104,112}; Fig. 1; [0073-0074, 0083]) is attached to the lid (152; Fig. 1; [0072-0075]). Regarding claim 3, modified Uhlig (by Sunohara) teaches all of the features of claim 2. Modified Uhlig (by Sunohara) further teaches wherein: the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) further comprises multiple projections ({106, 108}; Fig. 1; [0072-0074]) extending from the raised walls ({112}; Fig. 1; [0073-0074, 0083]); and the lid (152; Fig. 1; [0072-0075]) is attached to the projections ({106, 108}; Fig. 1; [0072-0075]) of the structural enclosure ({104, 112}; Fig. 1; [0073-0075, 0083]). Regarding claim 4, modified Uhlig (by Sunohara) teaches all of the features of claim 1. Modified Uhlig (by Sunohara) further teaches wherein the raised walls ({112}; Fig. 1; [0073-0074, 0083]) are as tall as or taller than the non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]). Regarding claim 5, modified Uhlig (by Sunohara) teaches all of the features of claim 1. Modified Uhlig (by Sunohara) further comprising at least one of: a material (110; Fig. 1; [0074, 0077, 0082]) at least partially filling one or more gaps between the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) and the electrical component (102; Fig. 1; [0073, 0080]); and a material (110; Fig. 1; [0074, 0077, 0082]) at least partially filling one or more gaps between the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) and the substrate (118; Fig. 1; [0079-0080]). Regarding claim 7, modified Uhlig (by Sunohara) teaches all of the features of claim 1. Modified Uhlig (by Sunohara) further teaches wherein the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) remains spaced apart from the electrical component (102; Fig. 1; [0073, 0080]) and does not contact the electrical component (102; Fig. 1; [0073, 0080]). Regarding claim 9, modified Uhlig (by Sunohara) teaches all of the features of claim 1. Modified Uhlig (by Sunohara) further teaches wherein: the non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]) are surface-mounted to a surface of the substrate (118; Fig. 1; [0079-0080]); and the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) is attached to the surface of the substrate (118; Fig. 1; [0079-0080]). Regarding claim 10, Uhlig teaches a method (see the entire document, specifically Fig. 1+; [0010+], and as cited below) comprising (see alternative rejection for claim 10 above): obtaining an electrical component (102; Fig. 1; [0073, 0080]) mounted to a substrate (118; Fig. 1; [0079-0080]), the electrical component (102; Fig. 1; [0073, 0080]) comprising (see below for “multiple non-collapsible solder columns”) (see [0080-0081]; electronic component 102 may be soldered on the carrier 118) physically and electrically connecting the electrical component to the substrate (118; Fig. 1; [0079-0080]); and attaching a structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) to the substrate (118; Fig. 1; [0079-0080]) such that the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) is positioned around lateral edges of the electrical component (102; Fig. 1; [0073, 0080]) , the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) comprising raised walls ({112}; Fig. 1; [0073-0074, 0083]) extending away from the substrate (118; Fig. 1; [0079-0080]) and surrounding the electrical component (102; Fig. 1; [0073, 0080]), the raised walls ({112}; Fig. 1; [0073-0074, 0083]) (see below for “configured to block foreign object debris from”) contacting the (see below for “non-collapsible solder columns”) (see [0080-0081]; electronic component 102 may be soldered on the carrier 118). As noted above, Uhlig does not expressly disclose “the electrical component comprising multiple non-collapsible solder columns physically and electrically connecting the electrical component to the substrate” and “the raised walls configured to block foreign object debris from contacting the non-collapsible solder columns”. However, in the analogous art, Sunohara teaches a wiring board for use in mounting an electronic component such as a semiconductor element (chip) thereon ([0002]), wherein (Fig. 1+; [0090+]) a chip (1; Fig. 2; [0042]) is physically and electrically connected to wiring board (10) through solder balls (45; Figs. 2, 4 [0045]) It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Sunohara’s solder balls connection layer into Uhlig’s method, and thereby, modified Uhlig’s (by Sunohara) method will have obtaining an electrical component (102; Fig. 1; [0073, 0080]) mounted to a substrate (118; Fig. 1; [0079-0080]), the electrical component (102; Fig. 1; [0073, 0080]) comprising multiple non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]) physically and electrically connecting the electrical component to the substrate (118; Fig. 1; [0079-0080]); and attaching a structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) to the substrate (118; Fig. 1; [0079-0080]) such that the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) is positioned around lateral edges of the electrical component (102; Fig. 1; [0073, 0080]), the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) comprising raised walls ({112}; Fig. 1; [0073-0074, 0083]) extending away from the substrate (118; Fig. 1; [0079-0080]) and surrounding the electrical component (102; Fig. 1; [0073, 0080]), the raised walls ({112}; Fig. 1; [0073-0074, 0083]) (see below for “configured to block foreign object debris from”) contacting the non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]). The ordinary artisan would have been motivated to modify Uhlig in the manner set forth above, at least, because this inclusion provides multiple solder balls to connect the chip to the substrate (Sunohara [0045]), which provides multiple solder structures between the chip and substrate which helps increase the reliability of the electrical connection. In regards “the raised walls configured to block foreign object debris from contacting the non-collapsible solder columns” (emphasis added), per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, modified Uhlig (by Sunohara) teaches the method of claim 1 as detailed above. Thus, modified Uhlig (by Sunohara) teaches all of the structural elements of the claimed method, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 11, modified Uhlig (by Sunohara) teaches all of the features of claim 10. Modified Uhlig (by Sunohara) further teaches wherein: the electrical component (102; Fig. 1; [0073, 0080]) further comprises a semiconductor die (102; Fig. 1; [0073, 0080]) and a lid (152; Fig. 1; [0072-0075]), the lid (152; Fig. 1; [0072-0075]) in thermal contact (see [0027, 0042, 0074], where 110 is a soft encapsulant ([0074]), and an equilibration of thermal load may be balanced out by such a soft encapsulant [0042])) with the semiconductor die (102; Fig. 1; [0073, 0080]); and the method further comprises attaching the structural enclosure ({104,112}; Fig. 1; [0073-0074, 0083]) to the lid (152; Fig. 1; [0072-0075]). Regarding claim 12, modified Uhlig (by Sunohara) teaches all of the features of claim 11. Modified Uhlig (by Sunohara) further teaches wherein: the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) further comprises multiple projections ({106, 108}; Fig. 1; [0072-0074]) extending from the raised walls ({112}; Fig. 1; [0073-0074, 0083]); and the lid (152; Fig. 1; [0072-0075]) is attached to the projections ({106, 108}; Fig. 1; [0072-0075]) of the structural enclosure ({104, 112}; Fig. 1; [0073-0075, 0083]). Regarding claim 13, modified Uhlig (by Sunohara) teaches all of the features of claim 10. Modified Uhlig (by Sunohara) further teaches wherein the raised walls ({112}; Fig. 1; [0073-0074, 0083]) are as tall as or taller than the non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]). Regarding claim 14, modified Uhlig (by Sunohara) teaches all of the features of claim 10. Modified Uhlig (by Sunohara) further comprising at least one of: using a material (110; Fig. 1; [0074, 0077, 0082]) at least partially filling one or more gaps between the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) and the electrical component (102; Fig. 1; [0073, 0080]); and using a material (110; Fig. 1; [0074, 0077, 0082]) at least partially filling one or more gaps between the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) and the substrate (118; Fig. 1; [0079-0080]). Regarding claim 16, modified Uhlig (by Sunohara) teaches all of the features of claim 10. Modified Uhlig (by Sunohara) further teaches wherein the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) remains spaced apart from the electrical component (102; Fig. 1; [0073, 0080]) and does not contact the electrical component (102; Fig. 1; [0073, 0080]). Regarding claim 18, modified Uhlig (by Sunohara) teaches all of the features of claim 10. Modified Uhlig (by Sunohara) further teaches wherein: the non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]) are surface-mounted to a surface of the substrate (118; Fig. 1; [0079-0080]); and the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) is attached to the surface of the substrate (118; Fig. 1; [0079-0080]). Regarding claim 19, Uhlig teaches an apparatus (see the entire document, specifically Fig. 1+; [0010+], and as cited below) comprising (see alternative rejection for claim 19 above): a structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) configured to be mounted to a substrate (118; Fig. 1; [0079-0080]) and positioned around lateral edges of an electrical component (102; Fig. 1; [0073, 0080]) mounted to the substrate (118; Fig. 1; [0079-0080]); wherein the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) comprises raised walls ({112}; Fig. 1; [0073-0074, 0083]) configured to surround the electrical component (102; Fig. 1; [0073, 0080]), the raised walls ({112}; Fig. 1; [0073-0074, 0083]) (see below for “configured to block foreign object debris from”) contacting (see below for “non-collapsible solder columns”) (see [0080-0081]; electronic component 102 may be soldered on the carrier 118) of the electrical component (102; Fig. 1; [0073, 0080]). As noted above, Uhlig does not expressly disclose “the raised walls configured to block foreign object debris from contacting non-collapsible solder columns”) of the electrical component”. However, in the analogous art, Sunohara teaches a wiring board for use in mounting an electronic component such as a semiconductor element (chip) thereon ([0002]), wherein (Fig. 1+; [0090+]) a chip (1; Fig. 2; [0042]) is physically and electrically connected to wiring board (10) through solder balls (45; Figs. 2, 4 [0045]) It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to incorporate Sunohara’s solder balls connection layer into Uhlig’s device, and thereby, modified Uhlig’s (by Sunohara) device will have wherein the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) comprises raised walls ({112}; Fig. 1; [0073-0074, 0083]) configured to surround the electrical component (102; Fig. 1; [0073, 0080]), the raised walls ({112}; Fig. 1; [0073-0074, 0083]) (see below for “configured to block foreign object debris from”) contacting non-collapsible solder columns (in view of Sunohara 45; Figs. 2, 4 [0045]; see also Uhlig see [0080-0081]) of the electrical component (102; Fig. 1; [0073, 0080]). The ordinary artisan would have been motivated to modify Uhlig in the manner set forth above, at least, because this inclusion provides multiple solder balls to connect the chip to the substrate (Sunohara [0045]), which provides multiple solder structures between the chip and substrate which helps increase the reliability of the electrical connection. In regards “the raised walls configured to block foreign object debris from contacting non-collapsible solder columns of the electrical component” (emphasis added), per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, modified Uhlig (by Sunohara) teaches the structure of claim 19 as detailed above. Thus, modified Uhlig (by Sunohara) teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent. Regarding claim 20, modified Uhlig (by Sunohara) teaches all of the features of claim 19. Modified Uhlig (by Sunohara) further comprising: multiple projections ({106, 108}; Fig. 1; [0072-0074]) extending from the raised walls ({112}; Fig. 1; [0073-0074, 0083]), the projections ({106, 108}; Fig. 1; [0072-0074]) configured to be attached to a lid (152; Fig. 1; [0072-0075]) of the electrical component (102; Fig. 1; [0073, 0080]). 4. Claims 6 and 15 are rejected under 35 U.S.C.103 as being unpatentable over Uhlig et al. (US 20210305109 A1; hereinafter Uhlig), in view of Sunohara (US 20110080713 A1; hereinafter Sunohara). in view of the following statement. Regarding claim 6, modified Uhlig (by Sunohara) teaches all of the features of claim 1. Modified Uhlig (by Sunohara) further teaches wherein the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) (see below for “comprises a three-dimensional (3D) printed structure”). As noted above, modified Uhlig (by Sunohara) does not expressly disclose “wherein the structural enclosure comprises a three-dimensional (3D) printed structure”. However, the Applicant has not presented persuasive evidence that the claimed “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without wherein the structural enclosure comprises a three-dimensional (3D) printed structure). Also, the Applicant has not shown that “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Instead, paragraph [0021] of the instant disclosure discloses other possible options such as “Also, the structural enclosure may be fabricated from one or more materials that are pre-qualified or pre-approved for use in certain applications or environments like in space-based or other applications, and the structural enclosure may be fabricated using common techniques like three-dimensional (3D) printing or other techniques” (emphasis added). Therefore, no rationale is given that the invention will not function without “wherein the structural enclosure comprises a three-dimensional (3D) printed structure”. Thus, the claimed “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is not critical to the invention. Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). PNG media_image1.png 18 19 media_image1.png Greyscale In view of the above, as there is no persuasive evidence that the particular configuration of “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is significant. Thus, the claimed limitation of “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is a matter of choice which a person of ordinary skill in the art would have found obvious as per MPEP §2144.04.IV(B) guideline. Therefore, the claimed limitation of “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is not patentable over Uhlig. Regarding claim 15, modified Uhlig (by Sunohara) teaches all of the features of claim 10. Modified Uhlig (by Sunohara) further teaches wherein the structural enclosure ({104, 112}; Fig. 1; [0073-0074, 0083]) (see below for “comprises a three-dimensional (3D) printed structure”). As noted above, modified Uhlig (by Sunohara) does not expressly disclose “wherein the structural enclosure comprises a three-dimensional (3D) printed structure”. However, the Applicant has not presented persuasive evidence that the claimed “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without wherein the structural enclosure comprises a three-dimensional (3D) printed structure). Also, the Applicant has not shown that “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” produces a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Instead, paragraph [0021] of the instant disclosure discloses other possible options such as “Also, the structural enclosure may be fabricated from one or more materials that are pre-qualified or pre-approved for use in certain applications or environments like in space-based or other applications, and the structural enclosure may be fabricated using common techniques like three-dimensional (3D) printing or other techniques” (emphasis added). Therefore, no rationale is given that the invention will not function without “wherein the structural enclosure comprises a three-dimensional (3D) printed structure”. Thus, the claimed “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is not critical to the invention. Examiner would like to note that MPEP §2144.04.IV(B) guideline, where change of shape is a Legal Precedent as Source of Supporting Rationale. See In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) (The court held that the configuration of the claimed disposable plastic nursing container was a matter of choice which a person of ordinary skill in the art would have found obvious absent persuasive evidence that the particular configuration of the claimed container was significant.). PNG media_image1.png 18 19 media_image1.png Greyscale In view of the above, as there is no persuasive evidence that the particular configuration of “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is significant. Thus, the claimed limitation of “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is a matter of choice which a person of ordinary skill in the art would have found obvious as per MPEP §2144.04.IV(B) guideline. Therefore, the claimed limitation of “wherein the structural enclosure comprises a three-dimensional (3D) printed structure” is not patentable over Uhlig. Response to Arguments Applicant's arguments filed in the “Applicant Arguments/Remarks Made in an Amendment” on 07/15/2026 have been fully considered, but they are not persuasive, because of the following: the Applicant's amendment of claims 1, 10, and 19 necessitated the shift in new grounds of rejection detailed in sections above. The shift in grounds of rejection renders the Applicant's arguments moot. Please see the analysis of rejection for claims above. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado, can be reached on 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /OMAR F MOJADDEDI/Examiner, Art Unit 2898
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Prosecution Timeline

Apr 26, 2023
Application Filed
May 04, 2026
Non-Final Rejection mailed — §102, §103
Jul 15, 2026
Response Filed
Sep 22, 2026
Final Rejection mailed — §102, §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+10.4%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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